📄 controller.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.ALL;
use ieee.std_logic_signed.ALL;
use ieee.std_logic_arith.all;
entity controller is
port(
clock1m: in std_logic;
clock1: in std_logic;
state:in std_logic_vector(4 downto 0);
data_outr16: out std_logic_vector(0 to 15);
data_outg16: out std_logic_vector(0 to 15);
score:out std_logic_vector(7 downto 0);
scan_line: buffer std_logic_vector(0 to 15);
win: out std_logic;
lost:buffer std_logic);
end entity controller;
architecture behavioral of controller is
type red is array(integer range 0 to 30) of std_logic_vector(0 to 15);
constant sigg:red:=("1110111101110110", --0
"0111110111011011", --1
"1110111101111011", --2
"0111110111111110", --3
"1111011101011101", --4
"1110110111110111", --5
"0111111101011011", --6
"1111101111111111", --7
"1111011101111011", --8
"1011110110110111", --9
"1101111100111101", --10
"1110101111110111", --11
"1111110101011011", --12
"1010111111111110", --13
"0111110111110111", --14
"1110101101011111", --15
"1101011111101111", --16
"1111101011111110", --17
"1101111101110101", --18
"0101111111111111", --19
"1011101111101111", --20
"1110111101111101", --21
"1011101111111110", --22
"1101111011111011", --23
"0110111111101111", --24
"1101111110111111", --25
"1011011111110111", --26
"0111111101111111", --27
"1101011011101111", --28
"1011110110111110", --29
"1110111111110111"); --30
constant sigr:red:=("1011111011111111", --0r
"1111110111111111", --1y
"1111111110111111", --2r
"1111111111111111", --3
"1111011111111111", --4y
"1111111111111111", --5
"1101101111111111", --6r2
"1101101011111111", --7r2y1
"1111111111111111", --8
"1111011111111111", --9r1
"0111110111110111", --10r3
"1111111111110111", --11y1
"1111111111111111", --12
"1111111111111111", --13
"1111011111111111", --14r1
"1111111111110111", --15r1
"1011111111101111", --16r1y1
"1111111111111111", --17
"1111011111111111", --18r1
"1111110111101111", --19r2
"1111111111111101", --20r1
"1111111111111111", --21
"1010111111111111", --22r1y1
"1111111111011111", --23r1
"1111110111111111", --24r1
"1111111111111111", --25
"1111111111111111", --26
"1110111111111111", --27r1
"1111111011111111", --28r1
"1111111111111111", --29
"1111110111111111"); --30r1
signal platelctg:std_logic_vector(0 to 15);
constant platelctr:std_logic_vector(0 to 15):="1111111111111111";
shared variable lct:integer range 0 to 15; --led数据
shared variable datab:integer range 0 to 30; --led数据批次
shared variable datasta:integer range 0 to 1;
begin
p1:process(clock1m,state) --行saomiao xinhao
variable i:integer range 0 to 30;
variable count:integer range 0 to 500;
begin
if(clock1m'event and clock1m='1')then
if(state(3)='1' and state(4)='0')then --控制盘子左右移动
if(count=500)then
platelctg<=platelctg(1 to 15)&platelctg(0);
count:=0;
else
count:=count+1;
end if;
end if;
if(state(4)='1' and state(3)='0')then
if(count=500)then
platelctg<=platelctg(15)&platelctg(0 to 14);
count:=0;
else
count:=count+1;
end if;
end if;
if((state(0)='1' or state(1)='1'))then
if scan_line="1111111111111110" then
scan_line<="0111111111111111";
lct:=0;
else
scan_line<=scan_line(15)& scan_line(0 to 14);
lct:=lct+1;
end if;
if(lct=15)then --扫描同步数据信号输出
data_outg16<=platelctg; --托盘行扫描不变
data_outr16<="1111111111111111";
else
i:=datab-lct;
if(lct<=datab)then --解决初始下落有一段空白问题
data_outr16<=sigr(i);
data_outg16<=sigg(i);
elsif(lct>datab and datasta=0)then
data_outr16<="1111111111111111";
data_outg16<="1111111111111111";
else
i:=datab-lct+30;
data_outr16<=sigr(i);
data_outg16<=sigg(i);
end if;
end if;
end if;
end if;
if((state(2)='1' or(state(0)='0' and state(1)='0' and state(2)='0')))then --异步停止1
lct:=0;
scan_line<="1111111111111110";
data_outr16<="1111111111111111";
data_outg16<="1111111111111111";
platelctg<="1111111001111111";
count:=0;
end if;
end process p1;
p3:process(clock1,state) --每秒扫描下移一行
variable plcttmp:std_logic; --保护盘子位置数据不丢失
variable j:integer range 0 to 30;
variable plct1:integer range 0 to 15; --盘子位置
variable plct2:integer range 0 to 15;
variable tmp1:std_logic_vector(0 to 15); --红灯判断
variable tmp2:std_logic_vector(0 to 15);
variable scoretmp:integer range 0 to 150;
variable sct1:std_logic_vector(0 to 3);
variable sct2:std_logic_vector(0 to 3);
begin
if(rising_edge(clock1))then
if(state(0)='1')then
if(datab<30)then --更改扫描输出数据段
datab:=datab+1;
else
datab:=0;
end if;
if(datab>=14)then --提取接住物品情况
datasta:=1;
j:=datab-14+1;
tmp1:=sigr(j) nor platelctg;
tmp2:=sigg(j) nor platelctg;
end if;
if(datab<14 and datasta=1)then
j:=datab-14+30+1;
tmp1:=sigr(j) nor platelctg;
tmp2:=sigg(j) nor platelctg;
end if;
if(datab<14 and datasta=0)then
tmp1:="0000000000000000";
tmp2:="0000000000000000";
end if;
end if;
if(((state(0)='0' and state(1)='0' and state(2)='0')or state(2)='1'))then --初始化赋值,异步停止2
datab:=0;
datasta:=0;
lost<='0';
scoretmp:=0;
win<='0';
end if;
for k in 0 to 15 loop --记录盘子位置
if(platelctg(k)='0')then
plct1:=k;
end if;
end loop;
for k in 0 to 15 loop
if(platelctg(k)='0' and plct1/=k)then
plct2:=k;
end if;
end loop;
if((tmp1(plct1)='1' and tmp2(plct1)='1')or(tmp1(plct2)='1' and tmp2(plct2)='1'))then --接住物品情况判断
scoretmp:=scoretmp+50;
elsif((tmp1(plct1)='1' and tmp2(plct1)='0')or(tmp1(plct2)='1' and tmp2(plct2)='0'))then
scoretmp:=0;
lost<='1';
elsif((tmp1(plct1)='0' and tmp2(plct1)='1')or(tmp1(plct2)='0' and tmp2(plct2)='1'))then
scoretmp:=scoretmp+1;
else
scoretmp:=scoretmp;
end if;
--分数输出
if(scoretmp<10)then
score<=conv_std_logic_vector(scoretmp,8);
else
sct1:=conv_std_logic_vector(scoretmp/10,4);
sct2:=conv_std_logic_vector(scoretmp-(scoretmp/10)*10,4);
score<=sct1 & sct2 ;
end if;
if(scoretmp>99)then
win<='1';
else
win<='0';
end if;
end if;
end process p3;
end behavioral; ⌨️ 快捷键说明
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