sys_sim.mdl

很优良的PID控制器设计仿真程序与模型,经过严格检验

Model {
  Name			  "sys_sim"
  Version		  2.09
  SimParamPage		  Solver
  SampleTimeColors	  off
  InvariantConstants	  off
  WideVectorLines	  off
  ShowLineWidths	  off
  PaperOrientation	  landscape
  PaperType		  usletter
  PaperUnits		  inches
  StartTime		  "0.0"
  StopTime		  "10.0"
  Solver		  ode45
  RelTol		  "1e-3"
  AbsTol		  "1e-6"
  Refine		  "1"
  MaxStep		  "auto"
  InitialStep		  "auto"
  FixedStep		  "auto"
  MaxOrder		  5
  OutputOption		  RefineOutputTimes
  OutputTimes		  "[]"
  LoadExternalInput	  off
  ExternalInput		  "[t, u]"
  SaveTime		  on
  TimeSaveName		  "tout"
  SaveState		  off
  StateSaveName		  "xout"
  SaveOutput		  on
  OutputSaveName	  "yout"
  LoadInitialState	  off
  InitialState		  "xInitial"
  SaveFinalState	  off
  FinalStateName	  "xFinal"
  LimitMaxRows		  off
  MaxRows		  "1000"
  Decimation		  "1"
  AlgebraicLoopMsg	  warning
  MinStepSizeMsg	  warning
  UnconnectedInputMsg	  warning
  UnconnectedOutputMsg	  warning
  UnconnectedLineMsg	  warning
  ConsistencyChecking	  off
  ZeroCross		  on
  SimulationMode	  normal
  RTWSystemTargetFile	  "grt.tlc"
  RTWInlineParameters	  off
  RTWRetainRTWFile	  off
  RTWTemplateMakefile	  "grt_vc.tmf"
  RTWMakeCommand	  "make_rtw"
  RTWGenerateCodeOnly	  off
  ExtModeMexFile	  "ext_comm"
  ExtModeBatchMode	  off
  BlockDefaults {
    Orientation		    right
    ForegroundColor	    black
    BackgroundColor	    white
    DropShadow		    off
    NamePlacement	    normal
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    normal
    FontAngle		    normal
    ShowName		    on
  }
  AnnotationDefaults {
    HorizontalAlignment	    center
    VerticalAlignment	    middle
    ForegroundColor	    black
    BackgroundColor	    white
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    normal
    FontAngle		    normal
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    normal
    FontAngle		    normal
  }
  System {
    Name		    "sys_sim"
    Location		    [178, 215, 542, 361]
    Open		    on
    ScreenColor		    white
    Block {
      BlockType		      Step
      Name		      "Step"
      Position		      [15, 15, 45, 45]
      Time		      "0"
      Before		      "0"
      After		      "1"
    }
    Block {
      BlockType		      Sum
      Name		      "Sum"
      Ports		      [2, 1, 0, 0, 0]
      Position		      [80, 25, 100, 45]
      FontName		      "Times New Roman"
      FontSize		      8
      Inputs		      "+-"
    }
    Block {
      BlockType		      TransferFcn
      Name		      "Transfer Fcn"
      Position		      [120, 17, 155, 53]
      FontName		      "Times New Roman"
      FontSize		      8
      Numerator		      "nn_c"
      Denominator	      "dd_c"
    }
    Block {
      BlockType		      TransferFcn
      Name		      "Transfer Fcn1"
      Position		      [180, 17, 215, 53]
      FontName		      "Times New Roman"
      FontSize		      8
      Numerator		      "nn_p"
      Denominator	      "dd_p"
    }
    Block {
      BlockType		      TransferFcn
      Name		      "Transfer Fcn2"
      Position		      [180, 87, 215, 123]
      Orientation	      left
      FontName		      "Times New Roman"
      FontSize		      8
      Numerator		      "nn_h"
      Denominator	      "dd_h"
    }
    Block {
      BlockType		      TransportDelay
      Name		      "Transport\nDelay"
      Position		      [250, 20, 290, 50]
      DelayTime		      "Td"
      InitialInput	      "0"
      BufferSize	      "1024"
    }
    Block {
      BlockType		      Outport
      Name		      "Out"
      Position		      [320, 25, 340, 45]
      Port		      "1"
      OutputWhenDisabled      held
      InitialOutput	      "0"
    }
    Line {
      SrcBlock		      "Transfer Fcn2"
      SrcPort		      1
      Points		      [-110, 0]
      DstBlock		      "Sum"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Step"
      SrcPort		      1
      DstBlock		      "Sum"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Sum"
      SrcPort		      1
      DstBlock		      "Transfer Fcn"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Transport\nDelay"
      SrcPort		      1
      Points		      [0, 0]
      Branch {
	Points			[0, 70]
	DstBlock		"Transfer Fcn2"
	DstPort			1
      }
      Branch {
	DstBlock		"Out"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Transfer Fcn1"
      SrcPort		      1
      DstBlock		      "Transport\nDelay"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Transfer Fcn"
      SrcPort		      1
      DstBlock		      "Transfer Fcn1"
      DstPort		      1
    }
  }
}