test.lst

受一篇网文启发

__text_start:
__start:
    001A EFCF      LDI	R28,0xFF
    001B E0D4      LDI	R29,4
    001C BFCD      OUT	0x3D,R28
    001D BFDE      OUT	0x3E,R29
    001E 51C0      SUBI	R28,0x10
    001F 40D0      SBCI	R29,0
    0020 EA0A      LDI	R16,0xAA
    0021 8308      STD	Y+0,R16
    0022 2400      CLR	R0
    0023 E0E0      LDI	R30,0
    0024 E0F1      LDI	R31,1
    0025 E011      LDI	R17,1
    0026 30E0      CPI	R30,0
    0027 07F1      CPC	R31,R17
    0028 F011      BEQ	0x002B
    0029 9201      ST	R0,Z+
    002A CFFB      RJMP	0x0026
    002B 8300      STD	Z+0,R16
    002C E3E4      LDI	R30,0x34
    002D E0F0      LDI	R31,0
    002E E0A0      LDI	R26,0
    002F E0B1      LDI	R27,1
    0030 E010      LDI	R17,0
    0031 33E4      CPI	R30,0x34
    0032 07F1      CPC	R31,R17
    0033 F021      BEQ	0x0038
    0034 95C8      LPM
    0035 9631      ADIW	R30,1
    0036 920D      ST	R0,X+
    0037 CFF9      RJMP	0x0031
    0038 D075      RCALL	_main
_exit:
    0039 CFFF      RJMP	_exit
FILE: E:\工作\数字功放\程序\test.c
(0001) #include <iom88v.h>
(0002) #include <macros.h>
(0003) #include <math.h>
(0004) 
(0005) 
(0006) 
(0007) //******************************************************/
(0008) void adc_init(void)
(0009) {
(0010)   ADCSRA = 0x00; 
_adc_init:
    003A 2422      CLR	R2
    003B 9220007A  STS	0x7A,R2
(0011)   ACSR = (1<<ACD);   
    003D E880      LDI	R24,0x80
    003E BF80      OUT	0x30,R24
(0012)   ADCSRA = (1<<ADEN)|(1<<ADPS2);
    003F E884      LDI	R24,0x84
    0040 9380007A  STS	0x7A,R24
    0042 9508      RET
(0013) }
(0014) //****************************************************/
(0015) void timer1_init(void)  
(0016) {
(0017)   
(0018)   
(0019)   TCCR1B = 0x00;
_timer1_init:
    0043 2422      CLR	R2
    0044 92200081  STS	0x81,R2
(0020)    
(0021)   TCNT1H = 0xFF; 
    0046 EF8F      LDI	R24,0xFF
    0047 93800085  STS	0x85,R24
(0022)   TCNT1L = 0x38;
    0049 E388      LDI	R24,0x38
    004A 93800084  STS	0x84,R24
(0023)   
(0024)   OCR1AH = 0x00; 
    004C 92200089  STS	0x89,R2
(0025)   OCR1AL = 0x00;
    004E 92200088  STS	0x88,R2
(0026)   
(0027)   OCR1BH = 0x00;  
    0050 9220008B  STS	0x8B,R2
(0028)   OCR1BL = 0x00;  
    0052 9220008A  STS	0x8A,R2
(0029)   
(0030)   ICR1H  = 0x01;
    0054 E081      LDI	R24,1
    0055 93800087  STS	0x87,R24
(0031)   ICR1L  = 0x8F;
    0057 E88F      LDI	R24,0x8F
    0058 93800086  STS	0x86,R24
(0032)   
(0033)   TCCR1A = (1<<COM1A1)|(1<<COM1B0)|(1<<COM1B1)|(1<<WGM11); 
    005A EB82      LDI	R24,0xB2
    005B 93800080  STS	0x80,R24
(0034)   TCCR1B = (1<<WGM13)|(1<<WGM12)|(1<<CS10);      
    005D E189      LDI	R24,0x19
    005E 93800081  STS	0x81,R24
(0035)   TIMSK1 = 0x20;
    0060 E280      LDI	R24,0x20
    0061 9380006F  STS	0x6F,R24
    0063 9508      RET
_timer1_capt_isr:
    0064 938A      ST	R24,-Y
    0065 939A      ST	R25,-Y
    0066 B78F      IN	R24,0x3F
    0067 938A      ST	R24,-Y
(0036) }
(0037) //*************************************************/
(0038) #pragma interrupt_handler timer1_capt_isr:11
(0039) void timer1_capt_isr(void)					
(0040) {
(0041)     ADMUX = 0x43;
    0068 E483      LDI	R24,0x43
    0069 9380007C  STS	0x7C,R24
(0042)     ADCSRA |= (1<<ADSC);
    006B 9180007A  LDS	R24,0x7A
    006D 6480      ORI	R24,0x40
    006E 9380007A  STS	0x7A,R24
(0043) 	
(0044) 	OCR1A = ADC & 0x03FF;
    0070 91800078  LDS	R24,0x78
    0072 91900079  LDS	R25,0x79
    0074 7093      ANDI	R25,3
    0075 93900089  STS	0x89,R25
    0077 93800088  STS	0x88,R24
(0045) 	OCR1B = ADC & 0x03FF;
    0079 91800078  LDS	R24,0x78
    007B 91900079  LDS	R25,0x79
    007D 7093      ANDI	R25,3
    007E 9390008B  STS	0x8B,R25
    0080 9380008A  STS	0x8A,R24
    0082 9189      LD	R24,Y+
    0083 BF8F      OUT	0x3F,R24
    0084 9199      LD	R25,Y+
    0085 9189      LD	R24,Y+
    0086 9518      RETI
(0046) }
(0047) //*******************************************************************
(0048) #pragma interrupt_handler adc_isr:22
(0049) void adc_isr(void)
(0050)  {
_adc_isr:
    0087 9518      RETI
(0051) 
(0052)  } 
(0053) /*********************************************************************
(0054)  延时
(0055) *********************************************************************/
(0056) void delay_1us(void)
(0057)  {
(0058)      asm("nop");
_delay_1us:
    0088 0000      NOP
    0089 9508      RET
_delay_nus:
  i                    --> R20
  n                    --> R22
    008A D03E      RCALL	push_gset2
    008B 01B8      MOVW	R22,R16
(0059)  }
(0060) void delay_nus(unsigned int n)
(0061)  {
(0062)      unsigned int i=0;
    008C 2744      CLR	R20
    008D 2755      CLR	R21
(0063)      for (i=0;i<n;i++) delay_1us();
    008E C003      RJMP	0x0092
    008F DFF8      RCALL	_delay_1us
    0090 5F4F      SUBI	R20,0xFF
    0091 4F5F      SBCI	R21,0xFF
    0092 1746      CP	R20,R22
    0093 0757      CPC	R21,R23
    0094 F3D0      BCS	0x008F
    0095 D02B      RCALL	pop_gset2
    0096 9508      RET
(0064)  }  
(0065) void delay_1ms(void)
(0066)  {
(0067) 	 unsigned int i;
(0068)      for (i=0;i<1140;i++);
_delay_1ms:
  i                    --> R16
    0097 2700      CLR	R16
    0098 2711      CLR	R17
    0099 C002      RJMP	0x009C
    009A 5F0F      SUBI	R16,0xFF
    009B 4F1F      SBCI	R17,0xFF
    009C 3704      CPI	R16,0x74
    009D E0E4      LDI	R30,4
    009E 071E      CPC	R17,R30
    009F F3D0      BCS	0x009A
    00A0 9508      RET
_delay_nms:
  i                    --> R20
  n                    --> R22
    00A1 D027      RCALL	push_gset2
    00A2 01B8      MOVW	R22,R16
(0069)  }  
(0070) void delay_nms(unsigned int n)
(0071)  {
(0072)      unsigned int i=0;
    00A3 2744      CLR	R20
    00A4 2755      CLR	R21
(0073)     for (i=0;i<n;i++) delay_1ms();
    00A5 C003      RJMP	0x00A9
    00A6 DFF0      RCALL	_delay_1ms
    00A7 5F4F      SUBI	R20,0xFF
    00A8 4F5F      SBCI	R21,0xFF
    00A9 1746      CP	R20,R22
    00AA 0757      CPC	R21,R23
    00AB F3D0      BCS	0x00A6
    00AC D014      RCALL	pop_gset2
    00AD 9508      RET
(0074)  }
(0075) //******************************************************************
(0076) void main(void)
(0077) {
(0078)   WDR(); 
_main:
    00AE 95A8      WDR
(0079)   WDTCSR = 0x1F; 
    00AF E18F      LDI	R24,0x1F
    00B0 93800060  STS	0x60,R24
(0080)   WDTCSR = 0x0F; 
    00B2 E08F      LDI	R24,0xF
    00B3 93800060  STS	0x60,R24
(0081)   WDR();
    00B5 95A8      WDR
(0082)                        
(0083)   DDRB |= (1<<PB1)|(1<<PB2);
    00B6 B184      IN	R24,0x04
    00B7 6086      ORI	R24,6
    00B8 B984      OUT	0x04,R24
(0084)     
(0085)   CLI();
    00B9 94F8      BCLR	7
(0086)   timer1_init();            
    00BA DF88      RCALL	_timer1_init
(0087)   adc_init(); 
    00BB DF7E      RCALL	_adc_init
(0088)   SEI();    
    00BC 9478      BSET	7
    00BD C001      RJMP	0x00BF
(0089) 
(0090)   while(1)
(0091)   {
(0092)   WDR();	
FILE: <library>
    00BE 95A8      WDR
    00BF CFFE      RJMP	0x00BE
    00C0 9508      RET
pop_gset2:
    00C1 E0E2      LDI	R30,2
    00C2 C00C      RJMP	pop
push_gset5:
    00C3 92FA      ST	R15,-Y
    00C4 92EA      ST	R14,-Y
push_gset4:
    00C5 92DA      ST	R13,-Y
    00C6 92CA      ST	R12,-Y
push_gset3:
    00C7 92BA      ST	R11,-Y
    00C8 92AA      ST	R10,-Y
push_gset2:
    00C9 937A      ST	R23,-Y
    00CA 936A      ST	R22,-Y
push_gset1:
    00CB 935A      ST	R21,-Y
    00CC 934A      ST	R20,-Y
    00CD 9508      RET
pop_gset1:
    00CE E0E1      LDI	R30,1
pop:
    00CF 9149      LD	R20,Y+
    00D0 9159      LD	R21,Y+
    00D1 FDE0      SBRC	R30,0
    00D2 9508      RET
    00D3 9169      LD	R22,Y+
    00D4 9179      LD	R23,Y+
    00D5 FDE1      SBRC	R30,1
    00D6 9508      RET
    00D7 90A9      LD	R10,Y+
    00D8 90B9      LD	R11,Y+
    00D9 FDE2      SBRC	R30,2
    00DA 9508      RET
    00DB 90C9      LD	R12,Y+
    00DC 90D9      LD	R13,Y+
    00DD FDE3      SBRC	R30,3
    00DE 9508      RET
    00DF 90E9      LD	R14,Y+
    00E0 90F9      LD	R15,Y+
    00E1 9508      RET