mc.v

来自「关于交通灯的汇编程序」· Verilog 代码 · 共 75 行

module mc(clk,clear,aout,bout,agreen,ared,bgreen,bred);
input clk,clear;
output [7:0] aout,bout;
output agreen,ared,bgreen,bred;
reg agreen,ayellow,ared,bgreen,byellow,bred;
reg [7:0] cnt;
assign aout=cnt;
assign bout=cnt;
always @(posedge clk)
 begin
    if (!clear)    cnt<=0;
    else
      begin
        if (cnt[7:4]==0)
          begin
            if (cnt[3:0]==0) 
              begin
                cnt[3:0]<=9;
                cnt[7:4]<=6;
              end
            else  
              begin 
                cnt[3:0]<=cnt[3:0]-1;
                cnt[7:4]<=cnt[7:4];
              end
          end
        else
          begin
            if (cnt[3:0]==0) 
              begin
                cnt[3:0]<=9;
                cnt[7:4]<=cnt[7:4]-1;
              end
            else  
              begin 
                cnt[3:0]<=cnt[3:0]-1;
                cnt[7:4]<=cnt[7:4];
              end
          end
      end
  end
always @(posedge clk)
begin
 if (cnt[7:0]<=8'b01101001&cnt[7:0]>8'b00110101) 
    begin
      agreen<=1;
      ared<=0;
      bgreen<=0;
      bred<=1;
    end
  else if (cnt[7:0]<=8'b00110101&cnt[7:0]>8'b00110000)
    begin
      agreen<=~agreen;
      ared<=0;
      bgreen<=0;
      bred<=1;
    end
  else if (cnt[7:0]<=8'b00110000&cnt[7:0]>8'd5)
    begin
      agreen<=0;
      ared<=1;
      bgreen<=1;
      bred<=0;
    end
  else if(cnt[7:0]<=8'd5&cnt[7:0]>=8'd0)
    begin
      agreen<=0;
      ared<=1;
      bgreen<=~bgreen;
      bred<=0;
    end
end
endmodule