📄 mc.rpt
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-- Equation name is 'cnt4', location is LC3_C31, type is buried.
cnt4 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = clear & cnt4 & !_LC1_C29 & !_LC7_C30
# clear & !cnt4 & !_LC1_C29 & _LC7_C30;
-- Node name is '~138~1' = 'cnt5~1'
-- Equation name is '~138~1', location is LC1_C24, type is buried.
-- synthesized logic cell
_LC1_C24 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = clear & _LC3_C29;
-- Node name is ':138' = 'cnt5'
-- Equation name is 'cnt5', location is LC4_C24, type is buried.
cnt5 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = clear & _LC3_C29;
-- Node name is '~137~1' = 'cnt6~1'
-- Equation name is '~137~1', location is LC1_C31, type is buried.
-- synthesized logic cell
_LC1_C31 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = clear & !_LC1_C29 & _LC6_C31
# clear & _LC1_C29 & _LC7_C30;
-- Node name is ':137' = 'cnt6'
-- Equation name is 'cnt6', location is LC7_C31, type is buried.
cnt6 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = clear & !_LC1_C29 & _LC6_C31
# clear & _LC1_C29 & _LC7_C30;
-- Node name is '~136~1' = 'cnt7~1'
-- Equation name is '~136~1', location is LC6_C36, type is buried.
-- synthesized logic cell
_LC6_C36 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = _LC2_C31 & _LC6_C36 & _LC8_C31
# !_LC2_C31 & !_LC6_C36 & _LC7_C30 & _LC8_C31
# _LC6_C36 & !_LC7_C30 & _LC8_C31;
-- Node name is ':136' = 'cnt7'
-- Equation name is 'cnt7', location is LC5_C31, type is buried.
cnt7 = DFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = cnt7 & _LC2_C31 & _LC8_C31
# !cnt7 & !_LC2_C31 & _LC7_C30 & _LC8_C31
# cnt7 & !_LC7_C30 & _LC8_C31;
-- Node name is '|lpm_add_sub:526|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_C30', type is buried
_LC8_C30 = LCELL( _EQ017);
_EQ017 = cnt1
# cnt0;
-- Node name is '|lpm_add_sub:526|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_C30', type is buried
_LC3_C30 = LCELL( _EQ018);
_EQ018 = cnt1
# cnt0
# cnt2;
-- Node name is '|lpm_add_sub:527|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_C31', type is buried
_LC2_C31 = LCELL( _EQ019);
_EQ019 = cnt5
# cnt4
# cnt6;
-- Node name is ':27'
-- Equation name is '_LC1_C29', type is buried
!_LC1_C29 = _LC1_C29~NOT;
_LC1_C29~NOT = LCELL( _EQ020);
_EQ020 = cnt7
# cnt6
# cnt5
# cnt4;
-- Node name is ':72'
-- Equation name is '_LC7_C30', type is buried
!_LC7_C30 = _LC7_C30~NOT;
_LC7_C30~NOT = LCELL( _EQ021);
_EQ021 = cnt3
# cnt0
# cnt2
# cnt1;
-- Node name is ':97'
-- Equation name is '_LC6_C31', type is buried
_LC6_C31 = LCELL( _EQ022);
_EQ022 = cnt5 & cnt6
# cnt4 & cnt6
# !cnt4 & !cnt5 & !cnt6 & _LC7_C30
# cnt6 & !_LC7_C30;
-- Node name is ':114'
-- Equation name is '_LC3_C29', type is buried
_LC3_C29 = LCELL( _EQ023);
_EQ023 = _LC1_C29 & _LC7_C30
# cnt4 & cnt5 & _LC7_C30
# !cnt4 & !cnt5 & _LC7_C30
# cnt5 & !_LC1_C29 & !_LC7_C30;
-- Node name is '~120~1'
-- Equation name is '~120~1', location is LC8_C31, type is buried.
-- synthesized logic cell
_LC8_C31 = LCELL( _EQ024);
_EQ024 = clear & !_LC1_C29;
-- Node name is ':175'
-- Equation name is '_LC5_C25', type is buried
!_LC5_C25 = _LC5_C25~NOT;
_LC5_C25~NOT = LCELL( _EQ025);
_EQ025 = !cnt3 & !cnt4
# !cnt1 & !cnt2 & !cnt4;
-- Node name is ':218'
-- Equation name is '_LC4_C30', type is buried
!_LC4_C30 = _LC4_C30~NOT;
_LC4_C30~NOT = LCELL( _EQ026);
_EQ026 = !cnt2 & !cnt3
# !cnt1 & !cnt3;
-- Node name is '~235~1'
-- Equation name is '~235~1', location is LC7_C25, type is buried.
-- synthesized logic cell
_LC7_C25 = LCELL( _EQ027);
_EQ027 = !cnt7 & !_LC5_C25
# !cnt6 & !cnt7
# !cnt5 & !cnt7;
-- Node name is ':235'
-- Equation name is '_LC8_C25', type is buried
_LC8_C25 = LCELL( _EQ028);
_EQ028 = cnt6 & _LC7_C25
# _LC4_C25 & _LC4_C30 & _LC7_C25;
-- Node name is '~313~1'
-- Equation name is '~313~1', location is LC2_C25, type is buried.
-- synthesized logic cell
_LC2_C25 = LCELL( _EQ029);
_EQ029 = cnt0 & !cnt2 & !cnt3
# cnt1 & !cnt2 & !cnt3
# cnt0 & !cnt1 & !cnt3
# !cnt1 & cnt2 & !cnt3;
-- Node name is '~313~2'
-- Equation name is '~313~2', location is LC4_C25, type is buried.
-- synthesized logic cell
_LC4_C25 = LCELL( _EQ030);
_EQ030 = cnt4 & cnt5;
-- Node name is ':313'
-- Equation name is '_LC6_C25', type is buried
_LC6_C25 = LCELL( _EQ031);
_EQ031 = !cnt6 & !cnt7 & _LC2_C25 & _LC4_C25;
-- Node name is '~392~1'
-- Equation name is '~392~1', location is LC4_C29, type is buried.
-- synthesized logic cell
_LC4_C29 = LCELL( _EQ032);
_EQ032 = cnt4 & cnt5 & !_LC7_C30
# !cnt4 & !cnt5 & !_LC4_C30;
-- Node name is ':392'
-- Equation name is '_LC6_C29', type is buried
!_LC6_C29 = _LC6_C29~NOT;
_LC6_C29~NOT = LCELL( _EQ033);
_EQ033 = cnt7
# cnt6
# _LC4_C29;
-- Node name is ':395'
-- Equation name is '_LC7_C29', type is buried
_LC7_C29 = LCELL( _EQ034);
_EQ034 = !_LC1_C29
# _LC4_C30;
-- Node name is '~478~1'
-- Equation name is '~478~1', location is LC5_C29, type is buried.
-- synthesized logic cell
_LC5_C29 = LCELL( _EQ035);
_EQ035 = !_LC1_C29 & !_LC6_C29
# _LC4_C30 & !_LC6_C29;
-- Node name is ':482'
-- Equation name is '_LC7_C32', type is buried
_LC7_C32 = DFFE( _EQ036, GLOBAL( clk), VCC, VCC, VCC);
_EQ036 = _LC5_C29 & !_LC6_C25 & _LC7_C32
# _LC6_C25 & !_LC7_C32
# _LC8_C25;
-- Node name is ':496'
-- Equation name is '_LC8_C29', type is buried
_LC8_C29 = DFFE( _EQ037, GLOBAL( clk), VCC, VCC, VCC);
_EQ037 = !_LC6_C25 & !_LC8_C25 & _LC8_C29
# !_LC5_C29 & !_LC6_C25 & !_LC8_C25;
-- Node name is ':511'
-- Equation name is '_LC2_C29', type is buried
_LC2_C29 = DFFE( _EQ038, GLOBAL( clk), VCC, VCC, VCC);
_EQ038 = !_LC1_C25 & !_LC2_C29 & !_LC7_C29
# !_LC1_C25 & _LC2_C29 & _LC7_C29
# !_LC1_C25 & _LC6_C29;
-- Node name is '~524~1'
-- Equation name is '~524~1', location is LC1_C25, type is buried.
-- synthesized logic cell
!_LC1_C25 = _LC1_C25~NOT;
_LC1_C25~NOT = LCELL( _EQ039);
_EQ039 = !_LC6_C25 & !_LC8_C25;
-- Node name is ':525'
-- Equation name is '_LC3_C25', type is buried
_LC3_C25 = DFFE( _EQ040, GLOBAL( clk), VCC, VCC, VCC);
_EQ040 = _LC6_C25
# _LC8_C25
# _LC3_C25 & _LC5_C29;
Project Information i:\v\mc.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:04
Timing SNF Extractor 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:07
Memory Allocated
-----------------
Peak memory allocated during compilation = 24,898K
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