📄 mc.rpt
字号:
19 - - D -- OUTPUT 0 1 0 0 aout6
18 - - C -- OUTPUT 0 1 0 0 aout7
136 - - - 30 OUTPUT 0 1 0 0 ared
135 - - - 29 OUTPUT 0 1 0 0 bgreen
27 - - E -- OUTPUT 0 1 0 0 bout0
26 - - E -- OUTPUT 0 1 0 0 bout1
23 - - D -- OUTPUT 0 1 0 0 bout2
22 - - D -- OUTPUT 0 1 0 0 bout3
31 - - F -- OUTPUT 0 1 0 0 bout4
30 - - F -- OUTPUT 0 1 0 0 bout5
29 - - E -- OUTPUT 0 1 0 0 bout6
28 - - E -- OUTPUT 0 1 0 0 bout7
132 - - - 26 OUTPUT 0 1 0 0 bred
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: i:\v\mc.rpt
mc
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - C 30 OR2 0 2 0 2 |lpm_add_sub:526|addcore:adder|pcarry1
- 3 - C 30 OR2 0 3 0 2 |lpm_add_sub:526|addcore:adder|pcarry2
- 2 - C 31 OR2 0 3 0 2 |lpm_add_sub:527|addcore:adder|pcarry2
- 1 - C 29 OR2 ! 0 4 0 8 :27
- 7 - C 30 OR2 ! 0 4 0 15 :72
- 6 - C 31 OR2 0 4 0 2 :97
- 3 - C 29 OR2 0 4 0 2 :114
- 8 - C 31 AND2 s 1 1 0 2 ~120~1
- 6 - C 36 DFFE +s 0 3 1 0 cnt7~1 (~136~1)
- 5 - C 31 DFFE + 0 3 1 4 cnt7 (:136)
- 1 - C 31 DFFE +s 1 3 1 0 cnt6~1 (~137~1)
- 7 - C 31 DFFE + 1 3 1 7 cnt6 (:137)
- 1 - C 24 DFFE +s 1 1 1 0 cnt5~1 (~138~1)
- 4 - C 24 DFFE + 1 1 1 7 cnt5 (:138)
- 4 - C 31 DFFE +s 1 2 1 0 cnt4~1 (~139~1)
- 3 - C 31 DFFE + 1 2 1 7 cnt4 (:139)
- 5 - C 36 DFFE +s 1 2 1 0 cnt3~1 (~140~1)
- 5 - C 30 DFFE + 1 2 1 4 cnt3 (:140)
- 2 - C 30 DFFE +s 1 2 1 0 cnt2~1 (~141~1)
- 6 - C 30 DFFE + 1 2 1 5 cnt2 (:141)
- 2 - C 36 DFFE +s 1 2 1 0 cnt1~1 (~142~1)
- 1 - C 30 DFFE + 1 2 1 6 cnt1 (:142)
- 5 - C 24 DFFE +s 1 0 1 0 cnt0~1 (~143~1)
- 2 - C 24 DFFE + 1 0 1 6 cnt0 (:143)
- 5 - C 25 OR2 ! 0 4 0 1 :175
- 4 - C 30 OR2 ! 0 3 0 4 :218
- 7 - C 25 OR2 s 0 4 0 1 ~235~1
- 8 - C 25 OR2 0 4 0 4 :235
- 2 - C 25 OR2 s 0 4 0 1 ~313~1
- 4 - C 25 AND2 s 0 2 0 2 ~313~2
- 6 - C 25 AND2 0 4 0 4 :313
- 4 - C 29 OR2 s 0 4 0 1 ~392~1
- 6 - C 29 OR2 ! 0 3 0 2 :392
- 7 - C 29 OR2 0 2 0 1 :395
- 5 - C 29 OR2 s 0 3 0 3 ~478~1
- 7 - C 32 DFFE + 0 3 1 0 :482
- 8 - C 29 DFFE + 0 3 1 0 :496
- 2 - C 29 DFFE + 0 3 1 0 :511
- 1 - C 25 AND2 s ! 0 2 0 1 ~524~1
- 3 - C 25 DFFE + 0 3 1 0 :525
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: i:\v\mc.rpt
mc
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 1/ 72( 1%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 20/144( 13%) 0/ 72( 0%) 7/ 72( 9%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 5/ 72( 6%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
E: 1/144( 0%) 0/ 72( 0%) 4/ 72( 5%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 2/ 72( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
30: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
31: 6/24( 25%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: i:\v\mc.rpt
mc
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 20 clk
Device-Specific Information: i:\v\mc.rpt
mc
** EQUATIONS **
clear : INPUT;
clk : INPUT;
-- Node name is 'agreen'
-- Equation name is 'agreen', type is output
agreen = _LC7_C32;
-- Node name is 'aout0'
-- Equation name is 'aout0', type is output
aout0 = _LC5_C24;
-- Node name is 'aout1'
-- Equation name is 'aout1', type is output
aout1 = _LC2_C36;
-- Node name is 'aout2'
-- Equation name is 'aout2', type is output
aout2 = _LC2_C30;
-- Node name is 'aout3'
-- Equation name is 'aout3', type is output
aout3 = _LC5_C36;
-- Node name is 'aout4'
-- Equation name is 'aout4', type is output
aout4 = _LC4_C31;
-- Node name is 'aout5'
-- Equation name is 'aout5', type is output
aout5 = _LC1_C24;
-- Node name is 'aout6'
-- Equation name is 'aout6', type is output
aout6 = _LC1_C31;
-- Node name is 'aout7'
-- Equation name is 'aout7', type is output
aout7 = _LC6_C36;
-- Node name is 'ared'
-- Equation name is 'ared', type is output
ared = _LC8_C29;
-- Node name is 'bgreen'
-- Equation name is 'bgreen', type is output
bgreen = _LC2_C29;
-- Node name is 'bout0'
-- Equation name is 'bout0', type is output
bout0 = cnt0;
-- Node name is 'bout1'
-- Equation name is 'bout1', type is output
bout1 = cnt1;
-- Node name is 'bout2'
-- Equation name is 'bout2', type is output
bout2 = cnt2;
-- Node name is 'bout3'
-- Equation name is 'bout3', type is output
bout3 = cnt3;
-- Node name is 'bout4'
-- Equation name is 'bout4', type is output
bout4 = cnt4;
-- Node name is 'bout5'
-- Equation name is 'bout5', type is output
bout5 = cnt5;
-- Node name is 'bout6'
-- Equation name is 'bout6', type is output
bout6 = cnt6;
-- Node name is 'bout7'
-- Equation name is 'bout7', type is output
bout7 = cnt7;
-- Node name is 'bred'
-- Equation name is 'bred', type is output
bred = _LC3_C25;
-- Node name is '~143~1' = 'cnt0~1'
-- Equation name is '~143~1', location is LC5_C24, type is buried.
-- synthesized logic cell
_LC5_C24 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = clear & !_LC5_C24;
-- Node name is ':143' = 'cnt0'
-- Equation name is 'cnt0', location is LC2_C24, type is buried.
cnt0 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = clear & !cnt0;
-- Node name is '~142~1' = 'cnt1~1'
-- Equation name is '~142~1', location is LC2_C36, type is buried.
-- synthesized logic cell
_LC2_C36 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = clear & cnt0 & _LC2_C36 & !_LC7_C30
# clear & !cnt0 & !_LC2_C36 & !_LC7_C30;
-- Node name is ':142' = 'cnt1'
-- Equation name is 'cnt1', location is LC1_C30, type is buried.
cnt1 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = clear & cnt0 & cnt1 & !_LC7_C30
# clear & !cnt0 & !cnt1 & !_LC7_C30;
-- Node name is '~141~1' = 'cnt2~1'
-- Equation name is '~141~1', location is LC2_C30, type is buried.
-- synthesized logic cell
_LC2_C30 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = clear & _LC2_C30 & !_LC7_C30 & _LC8_C30
# clear & !_LC2_C30 & !_LC7_C30 & !_LC8_C30;
-- Node name is ':141' = 'cnt2'
-- Equation name is 'cnt2', location is LC6_C30, type is buried.
cnt2 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = clear & cnt2 & !_LC7_C30 & _LC8_C30
# clear & !cnt2 & !_LC7_C30 & !_LC8_C30;
-- Node name is '~140~1' = 'cnt3~1'
-- Equation name is '~140~1', location is LC5_C36, type is buried.
-- synthesized logic cell
_LC5_C36 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = clear & _LC3_C30 & _LC5_C36
# clear & !_LC3_C30 & !_LC5_C36
# clear & _LC7_C30;
-- Node name is ':140' = 'cnt3'
-- Equation name is 'cnt3', location is LC5_C30, type is buried.
cnt3 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = clear & cnt3 & _LC3_C30
# clear & !cnt3 & !_LC3_C30
# clear & _LC7_C30;
-- Node name is '~139~1' = 'cnt4~1'
-- Equation name is '~139~1', location is LC4_C31, type is buried.
-- synthesized logic cell
_LC4_C31 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = clear & !_LC1_C29 & _LC4_C31 & !_LC7_C30
# clear & !_LC1_C29 & !_LC4_C31 & _LC7_C30;
-- Node name is ':139' = 'cnt4'
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