madcat100.v

来自「关于交通灯的汇编程序」· Verilog 代码 · 共 21 行

module  madcat100(clk,clear,add,sub,out);
input   clk,clear,add,sub;
output[7:0]  out;
reg[7:0] oreg;
assign out=oreg;
always @(posedge clk or negedge clear)
    begin
        if(!clear)        oreg<=8'h00;
     
          else if(add&&sub)     oreg<=oreg;
        
          else if(add) 
              		if(oreg>=99)  oreg<=0;
              		else     oreg<=oreg+1;
        
          else if(sub)    
           			if(oreg<=0)     oreg<=99;
           			else      oreg<=oreg-1;
    end
endmodule