davinci_mmc.c

The latest MontaVista Linux driver about SD/MMC code

/*
 * linux/drivers/mmc/davinci.c
 *
 * TI DaVinci MMC controller file
 *
 * Copyright (C) 2006 Texas Instruments.
 *
 * ----------------------------------------------------------------------------
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 * ----------------------------------------------------------------------------
 Modifications:
 ver. 1.0: Oct 2005, Purushotam Kumar   Initial version
 ver 1.1:  Nov  2005, Purushotam Kumar  Solved bugs
 ver 1.2:  Jan  2066, Purushotam Kumar   Added card remove insert support
 -
 *

 */

#include <linux/config.h>
#include <linux/module.h>
#include <linux/tty.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/blkdev.h>
#include <linux/device.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/hardware.h>
#include <linux/mmc/host.h>
#include <linux/mmc/card.h>
#include <linux/mmc/protocol.h>
#include <asm/arch/irqs.h>
#include <asm/arch/hardware.h>
#include <asm/hardware/clock.h>

#include "davinci_mmc.h"
#include <asm/arch/edma.h>


extern void davinci_clean_channel(int ch_no);

/* MMCSD Init clock in Hz in opendain mode */
#define MMCSD_INIT_CLOCK 		200000
#define DRIVER_NAME 			"mmc0"
#define MMCINT_INTERRUPT    		IRQ_MMCINT
#define MMCSD_REGS_BASE_ADDR  		DAVINCI_MMC_SD_BASE
#define TCINTEN 			(0x1<<20)

/* This macro could not be defined to 0 (ZERO) or -ve value.
 * This value is multiplied to "HZ"
 * while requesting for timer interrupt every time for probing card.
 */
#define MULTIPILER_TO_HZ 1

struct device mmc_dev;
struct clk *mmc_clkp = NULL;
mmcsd_config_def mmcsd_cfg = {
/* read write thresholds (in bytes) can be any power of 2 from 2 to 64 */
	32,
/* To use the DMA or not-- 1- Use DMA, 0-Interrupt mode */
	1
};

mmcsd_regs_base *mmcsd_regs;
static unsigned int mmc_input_clk = 0;

/* Used to identify whether card being used currently by linux core or not */
static unsigned int is_card_busy = 0;
/* used to identify whether card probe(detection) is currently in progress */
static unsigned int is_card_detect_progress = 0;
/* used to identify whether core is icurrently initilizing the card or not */
static unsigned int is_init_progress = 0;
/* used to identify whether core request has been queue up or
 * not because request has come when card detection/probe was in progress
 */
static unsigned int is_req_queued_up = 0;
/* data structure to queue one request */
static struct mmc_host *que_mmc_host = NULL;
/* data structure to queue one request */
static struct mmc_request *que_mmc_request = NULL;

/* tells whether card is initizlzed or not */
static unsigned int is_card_initialized = 0;
static unsigned int new_card_state = 0;	/* tells current state of card */

static DEFINE_SPINLOCK(mmc_lock);

static void mmc_davinci_start_command(struct mmc_davinci_host *host,
				      struct mmc_command *cmd)
{
	u32 cmd_reg = 0;
	u32 resp_type = 0;
	u32 cmd_type = 0;
	int byte_cnt = 0, i = 0;
	unsigned long flags;

	dev_dbg(&mmc_dev, "\nMMCSD : CMD%d, argument 0x%08x",
		cmd->opcode, cmd->arg);
	if (cmd->flags & MMC_RSP_SHORT)
		dev_dbg(&mmc_dev, ", 32-bit response");
	if (cmd->flags & MMC_RSP_LONG)
		dev_dbg(&mmc_dev, ", 128-bit response");
	if (cmd->flags & MMC_RSP_CRC)
		dev_dbg(&mmc_dev, ", CRC");
	if (cmd->flags & MMC_RSP_BUSY)
		dev_dbg(&mmc_dev, ", busy notification");
	else
		dev_dbg(&mmc_dev, ", No busy notification");
	dev_dbg(&mmc_dev, "\n");
	host->cmd = cmd;

	/* Protocol layer does not provide response type,
	 * but our hardware needs to know exact type, not just size!
	 */
	switch (cmd->flags & MMC_RSP_MASK) {
	case MMC_RSP_NONE:
		/* resp 0 */
		break;
	case MMC_RSP_SHORT:
		/* resp 1, resp 1b */
		/* OR resp 3!! (assume this if bus is set opendrain) */
		if (host->bus_mode == MMC_BUSMODE_OPENDRAIN) {
			resp_type = 3;
			if (cmd->opcode == 3)
				resp_type = 1;
		} else {
			resp_type = 1;
		}
		break;
	case MMC_RSP_LONG:
		/* resp 2 */
		resp_type = 2;
		break;
	}

	/* Protocol layer does not provide command type, but our hardware
	 * needs it!
	 * any data transfer means adtc type (but that information is not
	 * in command structure, so we flagged it into host struct.)
	 * However, telling bc, bcr and ac apart based on response is
	 * not foolproof:
	 * CMD0  = bc  = resp0  CMD15 = ac  = resp0
	 * CMD2  = bcr = resp2  CMD10 = ac  = resp2
	 *
	 * Resolve to best guess with some exception testing:
	 * resp0 -> bc, except CMD15 = ac
	 * rest are ac, except if opendrain
	 */

	if (host->data_dir) {
		cmd_type = DAVINCI_MMC_CMDTYPE_ADTC;
	} else if (resp_type == 0 && cmd->opcode != 15) {
		cmd_type = DAVINCI_MMC_CMDTYPE_BC;
	} else if (host->bus_mode == MMC_BUSMODE_OPENDRAIN) {
		cmd_type = DAVINCI_MMC_CMDTYPE_BCR;
	} else {
		cmd_type = DAVINCI_MMC_CMDTYPE_AC;
	}
	/* Set command Busy or not */
	if (cmd->flags & MMC_RSP_BUSY) {
		/*
		 * Linux core sending BUSY which is not defined for cmd 24
		 * as per mmc standard
		 */
		if (cmd->opcode != 24) {

			cmd_reg = cmd_reg | (1 << 8);
		}
	}

	/* Set command index */
	cmd_reg |= cmd->opcode;

	/* Setting initialize clock */
	if (cmd->opcode == 0) {
		cmd_reg = cmd_reg | (1 << 14);
	}

	/* Set for generating DMA Xfer event */
	if ((host->use_dma == 1) && (host->data != NULL)
	    && ((cmd->opcode == 18) || (cmd->opcode == 25)
		|| (cmd->opcode == 24) || (cmd->opcode == 17))) {
		cmd_reg = cmd_reg | (1 << 16);
	}

	/* Setting whether command involves data transfer or not */
	if (cmd_type == DAVINCI_MMC_CMDTYPE_ADTC) {
		cmd_reg = cmd_reg | (1 << 13);
	}

	/* Setting whether stream or block transfer */
	if (cmd->flags & MMC_DATA_STREAM) {
		cmd_reg = cmd_reg | (1 << 12);
	}

	/* Setting whether data read or write */
	if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
		cmd_reg = cmd_reg | (1 << 11);
	}

	/* Setting response type */
	cmd_reg = cmd_reg | (resp_type << 9);

	if (host->bus_mode == MMC_BUSMODE_PUSHPULL) {
		cmd_reg = cmd_reg | (1 << 7);
	}

	/* set Command timeout */
	mmcsd_regs->mmc_tor = 0xFFFF;

	/* Enable interrupt */
	if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
		if (host->use_dma != 1) {
			mmcsd_regs->mmc_im = (MMCSD_EVENT_EOFCMD |
					      MMCSD_EVENT_WRITE |
					      MMCSD_EVENT_ERROR_CMDCRC |
					      MMCSD_EVENT_ERROR_DATACRC |
					      MMCSD_EVENT_ERROR_CMDTIMEOUT |
					      MMCSD_EVENT_ERROR_DATATIMEOUT |
					      MMCSD_EVENT_BLOCK_XFERRED);
		} else {
			mmcsd_regs->mmc_im = (MMCSD_EVENT_EOFCMD |
					      MMCSD_EVENT_ERROR_CMDCRC |
					      MMCSD_EVENT_ERROR_DATACRC |
					      MMCSD_EVENT_ERROR_CMDTIMEOUT |
					      MMCSD_EVENT_ERROR_DATATIMEOUT |
					      MMCSD_EVENT_BLOCK_XFERRED);
		}
	} else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) {
		if (host->use_dma != 1) {
			mmcsd_regs->mmc_im = (MMCSD_EVENT_EOFCMD |
					      MMCSD_EVENT_READ |
					      MMCSD_EVENT_ERROR_CMDCRC |
					      MMCSD_EVENT_ERROR_DATACRC |
					      MMCSD_EVENT_ERROR_CMDTIMEOUT |
					      MMCSD_EVENT_ERROR_DATATIMEOUT |
					      MMCSD_EVENT_BLOCK_XFERRED);
		} else {
			mmcsd_regs->mmc_im = (MMCSD_EVENT_EOFCMD |
					      MMCSD_EVENT_ERROR_CMDCRC |
					      MMCSD_EVENT_ERROR_DATACRC |
					      MMCSD_EVENT_ERROR_CMDTIMEOUT |
					      MMCSD_EVENT_ERROR_DATATIMEOUT |
					      MMCSD_EVENT_BLOCK_XFERRED);
		}

	} else {
		mmcsd_regs->mmc_im = (MMCSD_EVENT_EOFCMD |
				      MMCSD_EVENT_ERROR_CMDCRC |
				      MMCSD_EVENT_ERROR_DATACRC |
				      MMCSD_EVENT_ERROR_CMDTIMEOUT |
				      MMCSD_EVENT_ERROR_DATATIMEOUT);

	}

	/*
	 * It is required by controoler b4 WRITE command that
	 * FIFO should be populated with 32 bytes
	 */
	if ((host->data_dir == DAVINCI_MMC_DATADIR_WRITE) &&
	    (cmd_type == DAVINCI_MMC_CMDTYPE_ADTC) && (host->use_dma != 1)) {
		byte_cnt = mmcsd_cfg.rw_threshold;
		host->bytes_left -= mmcsd_cfg.rw_threshold;
		for (i = 0; i < (byte_cnt / 4); i++) {
			mmcsd_regs->mmc_dxr = *host->buffer;
			host->buffer++;
		}
	}

	if (cmd->opcode == 7) {
		spin_lock_irqsave(&mmc_lock, flags);
		new_card_state = 1;
		is_card_initialized = 1;
		host->old_card_state = new_card_state;
		is_init_progress = 0;
		spin_unlock_irqrestore(&mmc_lock, flags);
	}
	if (cmd->opcode == 1) {
		spin_lock_irqsave(&mmc_lock, flags);
		is_init_progress = 1;
		spin_unlock_irqrestore(&mmc_lock, flags);
	}

	host->is_core_command = 1;
	mmcsd_regs->mmc_arghl = cmd->arg;
	mmcsd_regs->mmc_cmd = cmd_reg;

}

static void mmc_davinci_dma_cb(int lch, u16 ch_status, void *data)
{
	int sync_dev = 0;
	struct mmc_davinci_host *host = (struct mmc_davinci_host *)data;

	if (DMA_COMPLETE == ch_status) {

		if (host->cmd == NULL && host->data == NULL) {
			if (host->data_dir == DAVINCI_MMC_DATADIR_READ) {
				sync_dev = DAVINCI_DMA_MMCTXEVT;
			} else {
				sync_dev = DAVINCI_DMA_MMCRXEVT;
			}
			dev_dbg(&mmc_dev,
				"Interrupt from DMA when no request has been made\n");
			davinci_stop_dma(sync_dev);
			return;
		}

		if (host->data_dir == DAVINCI_MMC_DATADIR_READ) {
			sync_dev = DAVINCI_DMA_MMCTXEVT;	/* Write */
		} else {
			sync_dev = DAVINCI_DMA_MMCRXEVT;	/* Read */
		}
		davinci_stop_dma(sync_dev);
	} else {
		/* Handing of Event missed interreupt from DMA */
		dev_dbg(&mmc_dev,
			"Event miss interrupt has been generated by DMA\n");
		if (host->data_dir == DAVINCI_MMC_DATADIR_READ) {
			sync_dev = DAVINCI_DMA_MMCTXEVT;	/* Write */
		} else {
			sync_dev = DAVINCI_DMA_MMCRXEVT;	/* Read */
		}
		davinci_clean_channel(sync_dev);
	}
}

static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
					  struct mmc_request *req)
{
	const char *dev_name;
	int sync_dev, r, edma_ch = 0, tcc = 0;
	unsigned char i, j;
	unsigned short acnt, bcnt, ccnt;
	unsigned int src_port, dst_port, temp_ccnt;
	enum address_mode mode_src, mode_dst;
	enum fifo_width fifo_width_src, fifo_width_dst;
	unsigned short src_bidx, dst_bidx;
	unsigned short src_cidx, dst_cidx;
	unsigned short bcntrld;
	enum sync_dimension sync_mode;
	edmacc_paramentry_regs temp;
	enum dma_event_q queue_no = EVENTQ_0;
	int edma_chan_num;
	unsigned int num_eight_words = (req->data->blocks * 512) / 32;
	static unsigned int option_read = 0;
	static unsigned int option_write = 0;
	static unsigned char dma_read_req = 1;
	static unsigned char dma_write_req = 1;

#define MAX_C_CNT		64000

	if ((req->data->flags & MMC_DATA_WRITE)) {
		sync_dev = DAVINCI_DMA_MMCTXEVT;	/* Write */
		dev_name = "MMC_WRITE";

		if (dma_write_req) {
			r = davinci_request_dma(sync_dev, dev_name,
						mmc_davinci_dma_cb, host,
						&edma_ch, &tcc, queue_no);
			if (r != 0) {
				dev_dbg(&mmc_dev,
					"MMC: davinci_request_dma() failed with %d\n",
r);
				return r;
			}
			dma_write_req = 0;
		}
	} else {
		sync_dev = DAVINCI_DMA_MMCRXEVT;	/* Read */
		dev_name = "MMC_READ";
		if (dma_read_req) {
			r = davinci_request_dma(sync_dev, dev_name,
						mmc_davinci_dma_cb, host,
						&edma_ch, &tcc, queue_no);
			if (r != 0) {
				dev_dbg(&mmc_dev,
					"MMC: davinci_request_dma() failed with %d\n",
					r);
				return r;
			}
			dma_read_req = 0;
		}
	}

	if ((req->data->flags & MMC_DATA_WRITE)) {
		/* AB Sync Transfer */
		/* Acnt =32, Bcnt= , Cnt=1 */

		sync_dev = DAVINCI_DMA_MMCTXEVT;	/* Write */
		acnt = 4;
		bcnt = 8;
		if (num_eight_words > MAX_C_CNT) {
			temp_ccnt = MAX_C_CNT;
			ccnt = temp_ccnt;
		} else {
			ccnt = num_eight_words;
			temp_ccnt = ccnt;
		}

		src_port = (unsigned int)virt_to_phys(req->data->req->buffer);
		mode_src = INCR;
		fifo_width_src = W8BIT;	/* It's not cared as modeDsr is INCR */
		src_bidx = 4;
		src_cidx = 32;