⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 bfsk_ricianfading_ber.mdl

📁 Simulink_BFSK_RicianFading,simulink环境下RicianFading的BFSK误码率仿真
💻 MDL
📖 第 1 页 / 共 2 页
字号:
	      SuppressErrorStatus     off
	      IncludeFileDelimiter    "Auto"
	      ERTCustomFileBanners    off
	      SupportAbsoluteTime     on
	      LogVarNameModifier      "rt_"
	      MatFileLogging	      on
	      MultiInstanceERTCode    off
	      SupportNonFinite	      on
	      SupportComplex	      on
	      PurelyIntegerCode	      off
	      SupportContinuousTime   on
	      SupportNonInlinedSFcns  on
	      EnableShiftOperators    on
	      ParenthesesLevel	      "Nominal"
	      ExtMode		      off
	      ExtModeStaticAlloc      off
	      ExtModeTesting	      off
	      ExtModeStaticAllocSize  1000000
	      ExtModeTransport	      0
	      ExtModeMexFile	      "ext_comm"
	      RTWCAPISignals	      off
	      RTWCAPIParams	      off
	      RTWCAPIStates	      off
	      GenerateASAP2	      off
	    }
	    PropName		    "Components"
	  }
	}
	hdlcoderui.hdlcc {
	  $ObjectID		  11
	  Description		  "HDL Coder custom configuration component"
	  Version		  "1.2.0"
	  Name			  "HDL Coder"
	  Array {
	    Type		    "Cell"
	    Dimension		    1
	    Cell		    ""
	    PropName		    "HDLConfigFile"
	  }
	  HDLCActiveTab		  "0"
	}
	PropName		"Components"
      }
      Name		      "Configuration"
      SimulationMode	      "normal"
      CurrentDlgPage	      "Solver"
    }
    PropName		    "ConfigurationSets"
  }
  Simulink.ConfigSet {
    $PropName		    "ActiveConfigurationSet"
    $ObjectID		    1
  }
  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Arial"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  BlockParameterDefaults {
    Block {
      BlockType		      Constant
    }
    Block {
      BlockType		      FrameConversion
      OutFrame		      "Frame based"
    }
    Block {
      BlockType		      Ground
    }
    Block {
      BlockType		      Inport
      Port		      "1"
      UseBusObject	      off
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      LatchByDelayingOutsideSignal off
      LatchByCopyingInsideSignal off
      Interpolate	      on
    }
    Block {
      BlockType		      Outport
      Port		      "1"
      UseBusObject	      off
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
    }
    Block {
      BlockType		      Reshape
      OutputDimensionality    "1-D array"
      OutputDimensions	      "[1,1]"
    }
    Block {
      BlockType		      Rounding
      Operator		      "floor"
      SampleTime	      "-1"
    }
    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      SFunctionModules	      "''"
      PortCounts	      "[]"
    }
    Block {
      BlockType		      SubSystem
      ShowPortLabels	      on
      Permissions	      "ReadWrite"
      PermitHierarchicalResolution "All"
      TreatAsAtomicUnit	      off
      SystemSampleTime	      "-1"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
    Block {
      BlockType		      Sum
      IconShape		      "rectangular"
      Inputs		      "++"
      InputSameDT	      on
      OutDataTypeMode	      "Same as first input"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      LockScale		      off
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      TriggerPort
      TriggerType	      "rising"
      StatesWhenEnabling      "inherit"
      ShowOutputPort	      off
      OutputDataType	      "auto"
      SampleTimeType	      "triggered"
      SampleTime	      "1"
      ZeroCross		      on
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Arial"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Arial"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "BFSK_RicianFading_BER"
    Location		    [2, 82, 1014, 721]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "A4"
    PaperUnits		    "centimeters"
    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
    TiledPageScale	    1
    ShowPageBoundaries	    off
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Reference
      Name		      "AWGN\nChannel"
      Ports		      [1, 1]
      Position		      [460, 46, 555, 104]
      SourceBlock	      "commchan3/AWGN\nChannel"
      SourceType	      "AWGN Channel"
      ShowPortLabels	      on
      SystemSampleTime	      "-1"
      FunctionWithSeparateData off
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      seed		      "67"
      noiseMode		      "Signal to noise ratio  (SNR)"
      EbNodB		      "10"
      EsNodB		      "10"
      SNRdB		      "SNR"
      bitsPerSym	      "1"
      Ps		      "1"
      Tsym		      "1"
      variance		      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "Error Rate\nCalculation"
      Ports		      [2]
      Position		      [710, 251, 785, 304]
      SourceBlock	      "commsink2/Error Rate\nCalculation"
      SourceType	      "Error Rate Calculation"
      N			      "0"
      st_delay		      "0"
      cp_mode		      "Entire frame"
      subframe		      "[]"
      PMode		      "Workspace"
      WsName		      "xErrorRate3"
      RsMode2		      off
      stop		      off
      numErr		      "100"
      maxBits		      "1e6"
    }
    Block {
      BlockType		      Reference
      Name		      "M-FSK\nDemodulator\nBaseband"
      Ports		      [1, 1]
      Position		      [595, 52, 670, 98]
      SourceBlock	      "commdigbbndfm2/M-FSK\nDemodulator\nBaseband"
      SourceType	      "M-FSK Demodulator Baseband"
      M			      "2"
      OutType		      "Bit"
      Dec		      "Binary"
      freqSep		      "FrequencySeparation"
      numSamp		      "2"
      outDataType	      "double"
    }
    Block {
      BlockType		      Reference
      Name		      "M-FSK\nModulator\nBaseband"
      Ports		      [1, 1]
      Position		      [135, 50, 210, 100]
      SourceBlock	      "commdigbbndfm2/M-FSK\nModulator\nBaseband"
      SourceType	      "M-FSK Modulator Baseband"
      M			      "2"
      InType		      "Bit"
      Enc		      "Binary"
      freqSep		      "FrequencySeparation"
      phaseType		      "Continuous"
      numSamp		      "2"
      outDataType	      "double"
    }
    Block {
      BlockType		      Reference
      Name		      "Multipath Rayleigh\nFading Channel"
      Ports		      [1, 1]
      Position		      [285, 53, 365, 97]
      SourceBlock	      "commchan2/Multipath Rayleigh\nFading Channel"
      SourceType	      "Multipath Rayleigh Fading Channel"
      ShowPortLabels	      on
      SystemSampleTime	      "-1"
      FunctionWithSeparateData off
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      Fd		      "fd"
      simTs		      "1/(2*BitRate)"
      delayVec		      "0"
      gainVecdB		      "0"
      normGain		      on
      Seed		      "73"
    }
    Block {
      BlockType		      Reference
      Name		      "Random Integer\nGenerator"
      Ports		      [0, 1]
      Position		      [15, 53, 95, 97]
      SourceBlock	      "commrandsrc2/Random Integer\nGenerator"
      SourceType	      "Random Integer Generator"
      ShowPortLabels	      on
      SystemSampleTime	      "-1"
      FunctionWithSeparateData off
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      mul		      "2"
      seed		      "37"
      Ts		      "1/BitRate"
      frameBased	      on
      sampPerFrame	      "BitRate"
      orient		      off
      outDataType	      "double"
    }
    Block {
      BlockType		      Reference
      Name		      "Rician Fading\nChannel"
      Ports		      [1, 1]
      Position		      [275, 153, 355, 197]
      SourceBlock	      "commchan2/Rician Fading\nChannel"
      SourceType	      "Rician Fading Channel"
      ShowPortLabels	      on
      SystemSampleTime	      "-1"
      FunctionWithSeparateData off
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      K			      "1"
      Fd		      "fd"
      simTs		      "1/(2*BitRate)"
      delayVec		      "0"
      gainVecdB		      "0"
      Seed		      "79"
    }
    Block {
      BlockType		      Sum
      Name		      "Sum"
      Ports		      [2, 1]
      Position		      [420, 65, 440, 85]
      ShowName		      off
      IconShape		      "round"
      Inputs		      "|++"
      InputSameDT	      off
      OutDataTypeMode	      "Inherit via internal rule"
      SaturateOnIntegerOverflow	off
    }
    Line {
      SrcBlock		      "Random Integer\nGenerator"
      SrcPort		      1
      Points		      [10, 0]
      Branch {
	Labels			[1, 0]
	DstBlock		"M-FSK\nModulator\nBaseband"
	DstPort			1
      }
      Branch {
	Points			[0, 215]
	DstBlock		"Error Rate\nCalculation"
	DstPort			2
      }
    }
    Line {
      SrcBlock		      "AWGN\nChannel"
      SrcPort		      1
      DstBlock		      "M-FSK\nDemodulator\nBaseband"
      DstPort		      1
    }
    Line {
      SrcBlock		      "M-FSK\nDemodulator\nBaseband"
      SrcPort		      1
      Points		      [15, 0; 0, 190]
      DstBlock		      "Error Rate\nCalculation"
      DstPort		      1
    }
    Line {
      SrcBlock		      "M-FSK\nModulator\nBaseband"
      SrcPort		      1
      Points		      [25, 0]
      Branch {
	DstBlock		"Multipath Rayleigh\nFading Channel"
	DstPort			1
      }
      Branch {
	Points			[0, 100]
	DstBlock		"Rician Fading\nChannel"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Multipath Rayleigh\nFading Channel"
      SrcPort		      1
      DstBlock		      "Sum"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Rician Fading\nChannel"
      SrcPort		      1
      Points		      [70, 0]
      DstBlock		      "Sum"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Sum"
      SrcPort		      1
      DstBlock		      "AWGN\nChannel"
      DstPort		      1
    }
  }
}

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -