function.asm

本人下载的电力系统相关资料,具有极其重要的参考价值

//====================================================================
// Function:	Function.asm
// Data:		2005/1/24
// Author:		yuansheng
//====================================================================
.include  spce.inc
.include  OpMacro.inc
//.external _F_GetAddr;
//.external _F_RdResource
.external _F_Delay
.external _F_DelayLong
.external _G_Data
.external _GB_Flag
.external _GB_Wr_Addr_H
.external _GB_Wr_Addr_L
//.include  Subprogram.c
//.public	_G_Data
.public	_GB_RdData
.ram
.var  GB_Wr_Buf,GB_Rd_Buf,_GB_RdData;
//.iram
//	_GB_RdData:		.dw	 50	dup(0)
	
.code
//========================================================================
//	Function:		F_IO_Init
//	Description:	initialize the I/O and CPU clock
//					PD1(SCL),PD0(SDA) ----->output low
//	Parameters: 	None
//	Returns: 		None
//	Notes:
//========================================================================                       
.PUBLIC			_F_IO_Init
_F_IO_Init:
	//	r1=[P_IOB_Buffer]		
		r1=0x0003
		[P_IOB_Data]=r1
		
	//	r1=[P_IOB_Attrib]		
		r1=0x0003
		[P_IOB_Attrib]=r1		
		
	//	r1=[P_IOB_Dir]		
		r1=0x0003
		[P_IOB_Dir]=r1
		
//		r1=[P_IOB_Data]		
//		r1=0x0000
//		[P_IOB_Data]=r1
		retf
//========================================================================
//	Function:		_F_SCK
//	Description:	initialize the I/O and CPU clock
//					PD1(SCL),PD0(SDA) ----->output low
//	Parameters: 	None
//	Returns: 		None
//	Notes:
//========================================================================                       
.PUBLIC			_F_SCK
_F_SCK:		
		M_ClrSCL();
		M_Delay();
		M_Delay();
		M_SetSCL();
		M_Delay();
		M_Delay();
		M_ClrSCL();
		retf
//========================================================================
//	Function:		_F_ClrWatDog
//	Description:	initialize the I/O and CPU clock
//					PD1(SCL),PD0(SDA) ----->output low
//	Parameters: 	None
//	Returns: 		None
//	Notes:
//========================================================================                       
.PUBLIC			_F_ClrWatDog
_F_ClrWatDog:		
		r1= 0x0001
		[P_Watchdog_Clear]=r1
		retf
//====================================================================================
//	Function:		F_Write1Bit
//	Description:	Write 9 bit data
//	Parameters:		GB_Wr_Buf
//	Returns:		None
//	Notes:			
//====================================================================================
.PUBLIC			_F_Write9Bit
_F_Write9Bit:
		r4=0x09
?L_Loop:
		r1=		[GB_Wr_Buf]					
		r1&=0x0100
		jnz		?L_Set_SDA
		M_ClrSDA//							//SDA export '0'
		jmp		?L_Check
?L_Set_SDA:
		M_SetSDA//							//SDA export '1'
?L_Check:
		r1=		[GB_Wr_Buf]
		r1=		r1 lsl 1
		[GB_Wr_Buf]= r1							//the buffer shift left
		call	_F_SCK		
		r4-=1
		jnz		?L_Loop
		call	_F_ClrWatDog						
		retf		
//====================================================================================
//	Function:		F_Write16Bit
//	Description:	Write 16 bit data
//	Parameters:		GB_Wr_Buf
//	Returns:		None
//	Notes:			
//====================================================================================
.PUBLIC			_F_Write16Bit
_F_Write16Bit:
		r4=0x10
?L_Loop:
		r1=		[GB_Wr_Buf]					
		r1&=0x8000
		jnz		?L_Set_SDA
		M_ClrSDA//							//SDA export '0'
		jmp		?L_Check
?L_Set_SDA:
		M_SetSDA//							//SDA export '1'
?L_Check:
		r1=		[GB_Wr_Buf]
		r1=		r1 lsl 1
		[GB_Wr_Buf]= r1							//the buffer shift left
		call	_F_SCK		
		r4-=1
		jnz		?L_Loop
		call	_F_ClrWatDog						
		retf		
//====================================================================================
//	Function:		F_Write8Bit
//	Description:	Write 8 bit data
//	Parameters:		GB_Wr_Buf
//	Returns:		None
//	Notes:			
//====================================================================================
.PUBLIC			_F_Write8Bit
_F_Write8Bit:
		r4=0x08
?L_Loop:
		r1=		[GB_Wr_Buf]					
		r1&=0x8000
		jnz		?L_Set_SDA
		M_ClrSDA//							//SDA export '0'
		jmp		?L_Check
?L_Set_SDA:
		M_SetSDA//							//SDA export '1'
?L_Check:
		r1=		[GB_Wr_Buf]
		r1=		r1 lsl 1
		[GB_Wr_Buf]= r1							//the buffer shift left
		cmp		r4,1
		je		?L_EndSCK
		call	_F_SCK		
		r4-=1
		jmp		?L_Loop
?L_EndSCK:
		M_ClrSCL();
		M_Delay();
		M_Delay();
		M_SetSCL();
		call	_F_ClrWatDog
		nop					
//		M_SetSDA					
		retf
//====================================================================================
//	Function:		F_Read8Bit
//	Description:	read 8 bit data
//	Parameters:		None
//	Returns:		GB_Rd_Buf
//	Notes:			
//====================================================================================
.PUBLIC			_F_Read8Bit
_F_Read8Bit:
		r1=0x0000
		[GB_Rd_Buf]=r1	
		r4=0x08
		M_SetIO_Input//						//set PB0 input with pull-high
?L_Loop:
		cmp		r4,1
		je		?L_EndSCK_Read		
		call	_F_SCK
		jmp		?L_Read
?L_EndSCK_Read:
		M_ClrSCL();
		M_Delay();
		M_Delay();
		M_SetSCL();		
?L_Read:	
		r1=		[GB_Rd_Buf]
		r1=		r1 lsl 1
		[GB_Rd_Buf]= r1
		r1=		[P_IOB_Data]					//read the data	
		r1&=0x01
		r1|=[GB_Rd_Buf]
		[GB_Rd_Buf]=r1			
		r4-=1
		jnz		?L_Loop	
		M_SetIO_Output						//set PB0 output low 
//		M_ClrSCL();
		call	_F_ClrWatDog
//		M_SetSDA
		retf
//========================================================================
//	Function:		F_ByteWR
//	Description:	Write one byte to 24C01A 
//	Parameters: 	GB_Wr_Addr: address 
//					GB_Data: data to write
//	Returns: 		None
//	Notes:
//========================================================================		
.PUBLIC		_F_ByteWR	
_F_ByteWR:
		M_StartSignal//						//create Start Signal
		r1=0x0000
		[GB_Wr_Buf]=r1				 		//write command 					// + write the address of device and the command(write)				
		call	_F_Write9Bit					
		
		r1=		[_GB_Wr_Addr_L]
		[GB_Wr_Buf]= r1
		call	_F_Write16Bit				//	write the address of data
			
		r1=		[_G_Data]
		[GB_Wr_Buf]= r1
		call	_F_Write8Bit 			//write the data
		call	_F_Delay
		nop			 
		nop	
		M_StopSignal
		nop			
		nop			
?L_Wrend:
		retf
//========================================================================
//	Function:		F_SeqtRD
//	Description:	 read data from 24C01 sequentially
//	Parameters: 	GB_Wr_Addr: address 
//					GB_Rd_Range: the number of one group data
//	Returns: 		GB_Data: the head address of one group data
//	Notes:
//========================================================================		
.PUBLIC		_F_SeqtRD	
_F_SeqtRD:
		M_StartSignal//						//create Start Signal
		r1=0x0100
		[GB_Wr_Buf]=r1						// + write the address of device and the command(write)				
		call	_F_Write8Bit
		
		r1=		[_GB_Wr_Addr_L]
		[GB_Wr_Buf]= r1
		call	_F_Write16Bit				//	write the address of data
		M_Delay
		
		nop
		nop
		call	_F_Read8Bit		
		r1=		[GB_Rd_Buf]
		[_GB_RdData]=r1
//		cmp		r2, 4
//		jne		?L_ReadLoop
		call	_F_Delay
		M_StopSignal//						//create Stop Signal	
		
		retf		








		
//========================================================================
//	Function:		_F_EraseAll
//	Description:	 read data from 24C01 sequentially
//	Parameters: 	GB_Wr_Addr: address 
//					GB_Rd_Range: the number of one group data
//	Returns: 		GB_Data: the head address of one group data
//	Notes:
//========================================================================		
.PUBLIC		_F_EraseAll	
_F_EraseAll:
		nop
		nop
		M_StartSignal//						//create Start Signal
		r1=0x60
		[GB_Wr_Buf]=r1						// + write the address of device and the command(write)				
		call	_F_Write8Bit
				

		r1=		[_GB_Wr_Addr_H]
		[GB_Wr_Buf]= r1
//		call	_F_Write1Bit				//	write the address of data
		
		r1=		[_GB_Wr_Addr_L]
		[GB_Wr_Buf]= r1
		call	_F_Write16Bit				//	write the address of data
		nop
		nop
		call 	_F_DelayLong
		
		M_StopSignal						//create Stop Signal	
		retf
		
//========================================================================
//	Function:		_F_SeqWR
//	Description:	Write one byte to 24C01A 
//	Parameters: 	GB_Wr_Addr: address 
//					GB_Data: data to write
//	Returns: 		None
//	Notes:
//========================================================================		
.PUBLIC		_F_SeqWR	
_F_SeqWR:
		r1=0x00
		[_GB_Wr_Addr_L]=r1
		[_GB_Wr_Addr_H]=r1
//		call	_F_GetAddr;
?L_WrLoop:
		call	_F_ByteWR
		r1=[_GB_Flag]
		jne		?L_SeqWrRts
		r2= [_GB_Wr_Addr_L]
		r2+=1
		[_GB_Wr_Addr_L]=r2
		cmp		r2,0xffff
		jne		?L_WrLoop
//		r2=[_GB_Wr_Addr_L]
//		jnz		?L_WrLoop	
		r1= [_GB_Wr_Addr_H]
		jnz		?L_SeqWrRts
		r1+=1
		[_GB_Wr_Addr_H] =r1
		jmp		?L_WrLoop
?L_SeqWrRts:
		nop
		nop			
		retf