📄 encoder.lst
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C:\DSP\2XX\DSPTOOLS\CGT\6.63B\dspa.exe -v2xx -i..\include -s -l encoder.asm encoder.obj -tC:\WINDOWS\TEMP\encoder.tmp
TMS320C1x/C2x/C2xx/C5x COFF Assembler Beta Version 6.63 Mon Feb 9 04:52:54 1998
Copyright (c) 1987-1996 Texas Instruments Incorporated
encoder.asm PAGE 1
1 *******************************************************
2 * TMS320C2x/C2xx/C5x ANSI C Codegen Beta Version 6.63
3 *******************************************************
4 ; C:\DSP\2XX\DSPTOOLS\CGT\6.63B\dspac.exe -v2xx -i..\include ..\source\encoder.c C:\WINDOWS\TEMP\encoder.i
5 ; C:\DSP\2XX\DSPTOOLS\CGT\6.63B\dspopt.exe -v2xx -s -O2 C:\WINDOWS\TEMP\encoder.if C:\WINDOWS\TEMP\encoder
6 ; C:\DSP\2XX\DSPTOOLS\CGT\6.63B\dspcg.exe -v2xx -o -n -o -n -o C:\WINDOWS\TEMP\encoder.opt C:\WINDOWS\TEMP
7 .port
8 0000 .bss _encoder_position,2,1
9 .file "..\source\encoder.c"
10 .file "c:\dsp\2xx\dsptools\cgt\6.63b\stdlib.h"
11 .sym _size_t,0,14,13,16
12 .sym _wchar_t,0,4,13,16
13 .globl _atoi
14 .globl _atol
15 .globl _atof
16 .globl _strtod
17 .globl _strtol
18 .globl _strtoul
19
20 .stag __div_t,32
21 .member _quot,0,4,8,16
22 .member _rem,16,4,8,16
23 .eos
24 .sym _div_t,0,8,13,32,__div_t
25
26 .stag __ldiv_t,64
27 .member _quot,0,5,8,32
28 .member _rem,32,5,8,32
29 .eos
30 .sym _ldiv_t,0,8,13,64,__ldiv_t
31 .globl _div
32 .globl _ldiv
33 .globl _rand
34 .globl _srand
35 .globl _calloc
36 .globl _free
37 .globl _malloc
38 .globl _minit
39 .globl _realloc
40 .globl _abort
41 .globl _exit
42 .globl _atexit
43 .globl _abs
44 .globl _labs
45 .globl _qsort
46 .globl _bsearch
47 .globl _getenv
48 .globl _ti_sprintf
49 .file "c:\dsp\2xx\dsptools\cgt\6.63b\math.h"
50 .globl _asin
51 .globl _acos
52 .globl _atan
53 .globl _atan2
54 .globl _ceil
TMS320C1x/C2x/C2xx/C5x COFF Assembler Beta Version 6.63 Mon Feb 9 04:52:54 1998
Copyright (c) 1987-1996 Texas Instruments Incorporated
encoder.asm PAGE 2
55 .globl _cos
56 .globl _cosh
57 .globl _exp
58 .globl _fabs
59 .globl _floor
60 .globl _fmod
61 .globl _frexp
62 .globl _ldexp
63 .globl _log
64 .globl _log10
65 .globl _modf
66 .globl _pow
67 .globl _sin
68 .globl _sinh
69 .globl _sqrt
70 .globl _tan
71 .globl _tanh
72 .file "..\include\q15_div.h"
73 .globl _q15_div
74 .file "..\include\q15_atan.h"
75 .globl _q15_atan
76 .globl _q15p_atan
77 .file "..\include\evm_qep.h"
78 .globl _qep_rollover
79 .globl _qep_diff
80 .globl _QEP_GetIncr
81 .globl _QEP_Init
82 .file "c:\dsp\24x\code\encoder\monitor.h"
83 .globl _monitor
84 .globl _Encoder_MSG
85 .file "..\include\encoder.h"
86 2000 QEP_ROLLOVER .set 8192
87 .globl _encoder_position
88 .globl _Encoder_Init
89 .globl _Encoder_ZeroPosition
90 .globl _Encoder_MatchIncrPhase
91 .globl _Encoder_CalcPhase
92 .globl _Encoder_SamplePosition
93 .globl _Encoder_CalcPosition
94 .file "..\source\encoder.c"
95 0000 .text
96
97 .sym _Encoder_Init,_Encoder_Init,32,2,0
98 .globl _Encoder_Init
99
100 .func 58
101 ;>>>> void Encoder_Init(unsigned rollover)
102 ******************************************************
103 * FUNCTION DEF : _Encoder_Init
104 ******************************************************
105 0000 _Encoder_Init:
106
107 0000 LF1 .set 0
108
TMS320C1x/C2x/C2xx/C5x COFF Assembler Beta Version 6.63 Mon Feb 9 04:52:54 1998
Copyright (c) 1987-1996 Texas Instruments Incorporated
encoder.asm PAGE 3
109 0000 8aa0 POPD *+
110 0001 80a0 SAR AR0,*+
111 0002 8180 SAR AR1,*
112 0003 00ab LAR AR0,*+,AR3
113
114 .sym _rollover,-3+LF1,14,9,16
115 .line 2
116 *** 63 ----------------------- *(unsigned*)0x7032 = 6144u;
117 .line 6
118 ;>>>> ADCTRL1 = 0x1800; /* enable both ADC's */
119 0004 bf0b LARK AR3,28722
0005 7032
120 0006 ae80 SPLK #6144,*
0007 1800
121 *** 64 ----------------------- *(unsigned*)0x7032 |= 0x100u;
122 .line 7
123 ;>>>> ADCTRL1 |= 0x0100; /* clear interrupt flag */
124 0008 bf80 LACK 256
0009 0100
125 000a 6d80 OR *
126 000b 9080 SACL *
127 *** 65 ----------------------- *(unsigned*)0x7034 = 3u;
128 .line 8
129 ;>>>> ADCTRL2 = 0x0003; /* ADC_CLOCK = SYSCLK/10 = 1MHz */
130 000c b903 LACK 3
131 000d 7802 ADRK 2
132 000e 908a SACL * ,AR2
133 *** 70 ----------------------- QEP_Init(0u, rollover);
134 .line 13
135 ;>>>> QEP_Init(0x0,rollover); /* QEP counts Timer 2 */
136 000f bf0a LARK AR2,-3+LF1
0010 fffd
137 0011 8be0 MAR *0+
138 0012 1089 LAC * ,AR1
139 0013 90a0 SACL *+
140 0014 b900 LACK 0
141 0015 90a0 SACL *+
142 0016 7a80 CALL _QEP_Init
0017 0000!
143 0018 7c02 SBRK 2
144 *** 76 ----------------------- Encoder_MSG();
145 .line 19
146 ;>>>> Encoder_MSG(); /* turn encoder into zero position */
147 0019 7a80 CALL _Encoder_MSG
001a 0000!
148 *** 77 ----------------------- Encoder_ZeroPosition();
149 .line 20
150 ;>>>> Encoder_ZeroPosition(); /* detect zero position adjust counter */
151 001b 7a80 CALL _Encoder_ZeroPosition
001c 0023'
152 *** 78 ----------------------- Encoder_MatchIncrPhase();
153 .line 21
154 ;>>>> Encoder_MatchIncrPhase(); /* match counter (quadrant) and phase */
155 001d 7a80 CALL _Encoder_MatchIncrPhase
TMS320C1x/C2x/C2xx/C5x COFF Assembler Beta Version 6.63 Mon Feb 9 04:52:54 1998
Copyright (c) 1987-1996 Texas Instruments Incorporated
encoder.asm PAGE 4
001e 003b'
156 *** ----------------------- return;
157 001f EPI0_1:
158 .line 23
159 001f 7c02 SBRK 2
160 0020 0090 LAR AR0,*-
161 0021 7680 PSHD *
162 0022 ef00 RET
163
164 .endfunc 80,000000000H,1
165
166 .sym _Encoder_ZeroPosition,_Encoder_ZeroPosition,32,2,0
167 .globl _Encoder_ZeroPosition
168
169 .func 92
170 ;>>>> void Encoder_ZeroPosition(void)
171 ******************************************************
172 * FUNCTION DEF : _Encoder_ZeroPosition
173 ******************************************************
174 0023 _Encoder_ZeroPosition:
175
176 *** 95 ----------------------- *(unsigned*)0x7092 &= 0xffbfu;
177 .line 4
178 ;>>>> OCRB &= 0xFFBF; /* clear bit 6 */
179 0023 bf0b LARK AR3,28818
0024 7092
180 0025 bf80 LACK 65471
0026 ffbf
181 0027 8b8b MAR * ,AR3
182 0028 6e80 AND *
183 0029 9080 SACL *
184 *** 96 ----------------------- *(unsigned*)0x709c &= 0xbfffu;
185 .line 5
186 ;>>>> PCDATDIR &= 0xBFFF; /* clear bit 14 */
187 002a 780a ADRK 10
188 002b bf80 LACK 49151
002c bfff
189 002d 6e80 AND *
190 002e 9080 SACL *
191 002f L2:
192 *** -----------------------g2:
193 *** 97 ----------------------- if ( !(*(unsigned*)0x709c&0x40) ) goto g2;
194 .line 6
195 ;>>>> while ( !(PCDATDIR & 0x0040)); /* poll bit 6 */
196 002f bf0b LARK AR3,28828
0030 709c
197 0031 4980 BIT * ,9
198 0032 e200 BBZ L2
0033 002f'
199 *** 98 ----------------------- *(unsigned*)0x7405 = 0u;
200 .line 7
201 ;>>>> T2CNT = 0x0;
202 0034 bf0c LARK AR4,29701
0035 7405
TMS320C1x/C2x/C2xx/C5x COFF Assembler Beta Version 6.63 Mon Feb 9 04:52:54 1998
Copyright (c) 1987-1996 Texas Instruments Incorporated
encoder.asm PAGE 5
203 0036 b900 LACK 0
204 0037 8b8c MAR * ,AR4
205 0038 9080 SACL *
206 *** ----------------------- return;
207 0039 EPI0_2:
208 .line 8
209 0039 8b89 MAR * ,AR1
210 003a ef00 RET
211
212 .endfunc 99,000000000H,1
213
214 .sym _Encoder_MatchIncrPhase,_Encoder_MatchIncrPhase,32,2,0
215 .globl _Encoder_MatchIncrPhase
216
217 .func 109
218 ;>>>> void Encoder_MatchIncrPhase(void)
219 ;>>>> char c;
220 ;>>>> volatile int buffer[2];
221 ;>>>> volatile unsigned ubuffer[2];
222 ;>>>> do
223 ******************************************************
224 * FUNCTION DEF : _Encoder_MatchIncrPhase
225 ******************************************************
226 003b _Encoder_MatchIncrPhase:
227 003b 8aa0 POPD *+
228 003c 80a0 SAR AR0,*+
229 003d 8180 SAR AR1,*
230 003e b005 LARK AR0,5
231 003f 00e0 LAR AR0,*0+
232
233 .sym _buffer,1,52,1,32,,2
234 .sym _ubuffer,3,62,1,32,,2
235 0040 L4:
236 *** -----------------------g2:
237 *** 131 ----------------------- ubuffer[1] = Encoder_SamplePosition();
238 .line 23
239 ;>>>> ubuffer[1] = Encoder_SamplePosition();
240 0040 7a89 CALL _Encoder_SamplePosition,AR1
0041 0092'
241 0042 9080 SACL *
242 0043 108a LAC * ,AR2
243 0044 b204 LARK AR2,4
244 0045 8be0 MAR *0+
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