91x_enet.c

MCS-51的一个Free小型操作系统,在KeilC中下编译工作

/******************** 
* Original work (C) COPYRIGHT 2006 STMicroelectronics **************************
* Modifications (C) CopyRight 2006 Richard barry
* File Name          : 91x_enet.c
* Author             : MCD Application Team
* Date First Issued  : May 2006
* Description        : ENET library functions
********************************************************************************
* History:
* May 2006: v1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/


/* Includes ------------------------------------------------------------------*/
#include "FreeRTOS.h"
#include "task.h"
#include "91x_lib.h"
#include "string.h"  //include when using memcpy function

/* Include of other module interface headers ---------------------------------*/
/* Local includes ------------------------------------------------------------*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#ifndef NULL
#define NULL    (0)
#endif
/* Function return values */
#define ENET_OK  (1)
#define ENET_NOK (0)

/* PHY interface constants. */
#define STE100P_STATUS_REG				0x01
#define STE100P_CONTROL_REG				0x00
#define STE100P_LINK_ABILITY			0x05
#define STE100P_STATUS_LINKED			0x0004
#define STE100P_AUTO_NEGOTIATE_ABILITY	0x1000
#define STE100P_AUTO_NEGOTIATE_COMPLETE 0x20
#define STE100P_10HALF              	0x0020
#define STE100P_10FULL              	0x0040
#define STE100P_100HALF             	0x0080
#define STE100P_100FULL             	0x0100
#define STE100P_CTRL_FULL           	0x0100


/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
#define ENET_NUM_RX_BUFFERS 8

static ENET_DMADSCRBase  dmaTxDscrBase, dmaRxDscrBase[ ENET_NUM_RX_BUFFERS ];
static volatile u8 RxBuff[ ENET_NUM_RX_BUFFERS ][ENET_BUFFER_SIZE], TxBuff[ENET_BUFFER_SIZE];

/* Private function prototypes -----------------------------------------------*/
extern MEMCOPY_L2S_BY4();

/* Interface functions -------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/

/*******************************************************************************
* Function Name  : ENET_SetMACConfig(ENET_MACConfig * MAC_Config)
* Description    : MAC Control Register Configuration
* Input          : MAC_Config structure
* Output         : None
* Return         : None
*******************************************************************************/
void ENET_MACControlConfig(ENET_MACConfig *MAC_Config)
{
  /* ReceiveALL bit */
  if (MAC_Config->ReceiveALL==ENABLE) ENET_MAC->MCR |= MAC_MCR_RA;
  else ENET_MAC->MCR &=~MAC_MCR_RA;

  /* MIIPrescaler */
  ENET_MAC->MCR &=~(0x3<<24);
  if ((MAC_Config->MIIPrescaler) == MIIPrescaler_2)
  ENET_MAC->MCR |=0x1<<24;

  /* Loopback mode */
  if (MAC_Config->LoopbackMode==ENABLE)
  {
    ENET_MAC->MCR &=~MAC_MCR_LM;
    ENET_MAC->MCR |=0x1<<21;
    ENET_MAC->MCR &=~MAC_MCR_DRO;  /*enable frame reception during transmission*/
  }

  /* Address filtering mode */
  ENET_MAC->MCR &=~MAC_MCR_AFM;
  ENET_MAC->MCR |= MAC_Config->AddressFilteringMode;

  /* VLAN Filtering Mode */
  ENET_MAC->MCR = (MAC_Config->VLANFilteringMode)<<15;

  /*Wrong Frame Pass */
  if (MAC_Config->PassWrongFrame == ENABLE) ENET_MAC->MCR |=MAC_MCR_PWF;
  else ENET_MAC->MCR &=~MAC_MCR_PWF;

  /* Late Collision Retransmission*/
  if (MAC_Config->LateCollision == ENABLE) ENET_MAC->MCR |=MAC_MCR_ELC;
  else ENET_MAC->MCR &=~MAC_MCR_ELC;

  /* Broadcast Frame Reception */
  if (MAC_Config->BroadcastFrameReception == ENABLE) ENET_MAC->MCR |=MAC_MCR_DBF;
  else ENET_MAC->MCR &=~MAC_MCR_DBF;

  /* PacketRetry */
  if (MAC_Config->PacketRetry == ENABLE) ENET_MAC->MCR &=~MAC_MCR_DPR;
  else ENET_MAC->MCR |=MAC_MCR_DPR;

  /* RxFrameFiltering */
  if (MAC_Config->RxFrameFiltering == ENABLE) ENET_MAC->MCR |=MAC_MCR_RVFF;
  else ENET_MAC->MCR &=~MAC_MCR_RVFF;

  /* AutomaticPadRemoval */
  if (MAC_Config->AutomaticPadRemoval == ENABLE) ENET_MAC->MCR |=MAC_MCR_APR;
  else ENET_MAC->MCR &=~MAC_MCR_APR;

  /* DefferalCheck */
  if (MAC_Config->DeferralCheck == ENABLE) ENET_MAC->MCR |=MAC_MCR_DCE;
  else ENET_MAC->MCR &=~MAC_MCR_DCE;

}



/*******************************************************************************
* Function Name  : ENET_SetOperatingMode
* Description    : Sets the Operating mode
* Input          : ENET_OperatingMode:(see ENET_OperatingMode in 91x_enet.h)
* Output         : None
* Return         : None
*******************************************************************************/
portBASE_TYPE ENET_SetOperatingMode( void )
{
unsigned portLONG ulStatusReg, ulControlReg, ulLinkAbilityReg;

	/* Link status is latched, so read twice to get current value */
	ulStatusReg = ENET_MIIReadReg(0, STE100P_STATUS_REG);
	ulStatusReg = ENET_MIIReadReg(0, STE100P_STATUS_REG);

	if( !( ulStatusReg & STE100P_STATUS_LINKED ) )
	{	
		/* No Link. */
		return pdFAIL;
	}

	ulControlReg = ENET_MIIReadReg(0, STE100P_CONTROL_REG);
	if (ulControlReg & STE100P_AUTO_NEGOTIATE_ABILITY)
	{				
		/* AutoNegotiation is enabled. */
		if (!(ulStatusReg & STE100P_AUTO_NEGOTIATE_COMPLETE))
		{
			/* Auto-negotiation in progress. */
			return pdFAIL;				
		}		

		ulLinkAbilityReg = ENET_MIIReadReg(0, STE100P_LINK_ABILITY);
		if( ( ulLinkAbilityReg & STE100P_100FULL ) || ( ulLinkAbilityReg & STE100P_10FULL ) )
		{
			ENET_MAC->MCR |=MAC_MCR_FDM;   /* full duplex mode */
			ENET_MAC->MCR &=~MAC_MCR_DRO;  /* enable frame reception during transmission */
		}
		else
		{
			ENET_MAC->MCR &=~MAC_MCR_FDM; /* half duplex mode */
			ENET_MAC->MCR |=MAC_MCR_DRO;  /* disable frame reception during transmission */
		}
	}
	else
	{
		if( ulStatusReg & STE100P_CTRL_FULL )
		{
			ENET_MAC->MCR |=MAC_MCR_FDM;   /* full duplex mode */
			ENET_MAC->MCR &=~MAC_MCR_DRO;  /* enable frame reception during transmission */		
		}
		else
		{
			ENET_MAC->MCR &=~MAC_MCR_FDM; /* half duplex mode */
			ENET_MAC->MCR |=MAC_MCR_DRO;  /* disable frame reception during transmission */
		}
	}	
	
	return pdPASS;
}

/*******************************************************************************
* Function Name  : ENET_MIIWriteReg
* Description    : Writes a value on the PHY registers
* Input          : phyDev PHY device address
                 : phyReg PHY register to be written
*                : phyVal PHY register value
* Output         : None
* Return         : None
*******************************************************************************/
void ENET_MIIWriteReg (u8 phyDev, u8 phyReg, u32  phyVal)
{

  volatile u32 addr;
  volatile u32 res;     /* temporary result for address register status */
  volatile u32 timeout;

  /* Prepare the MII register address */
  addr = 0;
  addr |= ((phyDev<<11) & MAC_MII_ADDR_PHY_ADDR); /* set the PHY address */
  addr |= ((phyReg<<6) & MAC_MII_ADDR_MII_REG); /* select the corresponding register */
  addr |= MAC_MII_ADDR_MII_WRITE;  /* in write mode */
  addr |= MAC_MII_ADDR_MII_BUSY;

  /* Check for the Busy flag */
  timeout=0;
  do
  {
    timeout++;
    res = ENET_MAC->MIIA;
  } while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_WRITE_TO));

  /* Give the value to the MII data register */
  ENET_MAC->MIID = (phyVal & 0xFFFF);

  /* write the result value into the MII Address register */
  ENET_MAC->MIIA =addr;

  /* Check for the Busy flag */
  timeout=0;
  do
  {
    timeout++;
    res = ENET_MAC->MIIA;
  } while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_WRITE_TO));

}

/*******************************************************************************
* Function Name  : ENET_MIIReadReg
* Description    : Writes a value on the PHY
* Input          : phyDev PHY device address
*                : phyReg PHY register to be read
* Output         : None
* Return         : The read value (16 bits)
*******************************************************************************/
u32 ENET_MIIReadReg (u8 phyDev, u32 phyReg )
{

  u32 rValue;
  u32 addr;
  u32 res;     /* temporary result for address register status */
  u32 timeout; /* timeout value for read process */

  /* prepare the MII register address */
  addr = 0;
  addr |= ((phyDev<<11) & MAC_MII_ADDR_PHY_ADDR); /* set the PHY address */
  addr |= ((phyReg<<6) & MAC_MII_ADDR_MII_REG); /* select the corresponding register */
  addr &= ~(MAC_MII_ADDR_MII_WRITE);  /* ... in read mode */
  addr |= MAC_MII_ADDR_MII_BUSY;

  /* Check for the Busy flag */
  timeout = 0;

  do
  {
    timeout++;
    res = ENET_MAC->MIIA;
  } while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_READ_TO));

  /* write the result value into the MII Address register */
  ENET_MAC->MIIA = addr;

  /* Check for the Busy flag */
  timeout = 0;

  do
  {
    timeout++;
    res = ENET_MAC->MIIA;
  } while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_READ_TO));

  /* read the result value from data register*/
  rValue = ENET_MAC->MIID;

  return (rValue & 0x0000FFFF);
}

/*******************************************************************************
* Function Name  : ENET_RxDscrInit
* Description    : Initializes the Rx ENET descriptor chain. Single Descriptor
* Input          : None
* Output         : None
* Return         : None
*******************************************************************************/

void ENET_RxDscrInit(void)