📄 mcf523x_etpu.h

📁 MCS-51的一个Free小型操作系统,在KeilC中下编译工作
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#define MCF_ETPU_ECDTRSR_DTRS17          (0x00020000)#define MCF_ETPU_ECDTRSR_DTRS18          (0x00040000)#define MCF_ETPU_ECDTRSR_DTRS19          (0x00080000)#define MCF_ETPU_ECDTRSR_DTRS20          (0x00100000)#define MCF_ETPU_ECDTRSR_DTRS21          (0x00200000)#define MCF_ETPU_ECDTRSR_DTRS22          (0x00400000)#define MCF_ETPU_ECDTRSR_DTRS23          (0x00800000)#define MCF_ETPU_ECDTRSR_DTRS24          (0x01000000)#define MCF_ETPU_ECDTRSR_DTRS25          (0x02000000)#define MCF_ETPU_ECDTRSR_DTRS26          (0x04000000)#define MCF_ETPU_ECDTRSR_DTRS27          (0x08000000)#define MCF_ETPU_ECDTRSR_DTRS28          (0x10000000)#define MCF_ETPU_ECDTRSR_DTRS29          (0x20000000)#define MCF_ETPU_ECDTRSR_DTRS30          (0x40000000)#define MCF_ETPU_ECDTRSR_DTRS31          (0x80000000)/* Bit definitions and macros for MCF_ETPU_ECIOSR */#define MCF_ETPU_ECIOSR_CIOS0            (0x00000001)#define MCF_ETPU_ECIOSR_CIOS1            (0x00000002)#define MCF_ETPU_ECIOSR_CIOS2            (0x00000004)#define MCF_ETPU_ECIOSR_CIOS3            (0x00000008)#define MCF_ETPU_ECIOSR_CIOS4            (0x00000010)#define MCF_ETPU_ECIOSR_CIOS5            (0x00000020)#define MCF_ETPU_ECIOSR_CIOS6            (0x00000040)#define MCF_ETPU_ECIOSR_CIOS7            (0x00000080)#define MCF_ETPU_ECIOSR_CIOS8            (0x00000100)#define MCF_ETPU_ECIOSR_CIOS9            (0x00000200)#define MCF_ETPU_ECIOSR_CIOS10           (0x00000400)#define MCF_ETPU_ECIOSR_CIOS11           (0x00000800)#define MCF_ETPU_ECIOSR_CIOS12           (0x00001000)#define MCF_ETPU_ECIOSR_CIOS13           (0x00002000)#define MCF_ETPU_ECIOSR_CIOS14           (0x00004000)#define MCF_ETPU_ECIOSR_CIOS15           (0x00008000)#define MCF_ETPU_ECIOSR_CIOS16           (0x00010000)#define MCF_ETPU_ECIOSR_CIOS17           (0x00020000)#define MCF_ETPU_ECIOSR_CIOS18           (0x00040000)#define MCF_ETPU_ECIOSR_CIOS19           (0x00080000)#define MCF_ETPU_ECIOSR_CIOS20           (0x00100000)#define MCF_ETPU_ECIOSR_CIOS21           (0x00200000)#define MCF_ETPU_ECIOSR_CIOS22           (0x00400000)#define MCF_ETPU_ECIOSR_CIOS23           (0x00800000)#define MCF_ETPU_ECIOSR_CIOS24           (0x01000000)#define MCF_ETPU_ECIOSR_CIOS25           (0x02000000)#define MCF_ETPU_ECIOSR_CIOS26           (0x04000000)#define MCF_ETPU_ECIOSR_CIOS27           (0x08000000)#define MCF_ETPU_ECIOSR_CIOS28           (0x10000000)#define MCF_ETPU_ECIOSR_CIOS29           (0x20000000)#define MCF_ETPU_ECIOSR_CIOS30           (0x40000000)#define MCF_ETPU_ECIOSR_CIOS31           (0x80000000)/* Bit definitions and macros for MCF_ETPU_ECDTROSR */#define MCF_ETPU_ECDTROSR_DTROS0         (0x00000001)#define MCF_ETPU_ECDTROSR_DTROS1         (0x00000002)#define MCF_ETPU_ECDTROSR_DTROS2         (0x00000004)#define MCF_ETPU_ECDTROSR_DTROS3         (0x00000008)#define MCF_ETPU_ECDTROSR_DTROS4         (0x00000010)#define MCF_ETPU_ECDTROSR_DTROS5         (0x00000020)#define MCF_ETPU_ECDTROSR_DTROS6         (0x00000040)#define MCF_ETPU_ECDTROSR_DTROS7         (0x00000080)#define MCF_ETPU_ECDTROSR_DTROS8         (0x00000100)#define MCF_ETPU_ECDTROSR_DTROS9         (0x00000200)#define MCF_ETPU_ECDTROSR_DTROS10        (0x00000400)#define MCF_ETPU_ECDTROSR_DTROS11        (0x00000800)#define MCF_ETPU_ECDTROSR_DTROS12        (0x00001000)#define MCF_ETPU_ECDTROSR_DTROS13        (0x00002000)#define MCF_ETPU_ECDTROSR_DTROS14        (0x00004000)#define MCF_ETPU_ECDTROSR_DTROS15        (0x00008000)#define MCF_ETPU_ECDTROSR_DTROS16        (0x00010000)#define MCF_ETPU_ECDTROSR_DTROS17        (0x00020000)#define MCF_ETPU_ECDTROSR_DTROS18        (0x00040000)#define MCF_ETPU_ECDTROSR_DTROS19        (0x00080000)#define MCF_ETPU_ECDTROSR_DTROS20        (0x00100000)#define MCF_ETPU_ECDTROSR_DTROS21        (0x00200000)#define MCF_ETPU_ECDTROSR_DTROS22        (0x00400000)#define MCF_ETPU_ECDTROSR_DTROS23        (0x00800000)#define MCF_ETPU_ECDTROSR_DTROS24        (0x01000000)#define MCF_ETPU_ECDTROSR_DTROS25        (0x02000000)#define MCF_ETPU_ECDTROSR_DTROS26        (0x04000000)#define MCF_ETPU_ECDTROSR_DTROS27        (0x08000000)#define MCF_ETPU_ECDTROSR_DTROS28        (0x10000000)#define MCF_ETPU_ECDTROSR_DTROS29        (0x20000000)#define MCF_ETPU_ECDTROSR_DTROS30        (0x40000000)#define MCF_ETPU_ECDTROSR_DTROS31        (0x80000000)/* Bit definitions and macros for MCF_ETPU_ECIER */#define MCF_ETPU_ECIER_CIE0              (0x00000001)#define MCF_ETPU_ECIER_CIE1              (0x00000002)#define MCF_ETPU_ECIER_CIE2              (0x00000004)#define MCF_ETPU_ECIER_CIE3              (0x00000008)#define MCF_ETPU_ECIER_CIE4              (0x00000010)#define MCF_ETPU_ECIER_CIE5              (0x00000020)#define MCF_ETPU_ECIER_CIE6              (0x00000040)#define MCF_ETPU_ECIER_CIE7              (0x00000080)#define MCF_ETPU_ECIER_CIE8              (0x00000100)#define MCF_ETPU_ECIER_CIE9              (0x00000200)#define MCF_ETPU_ECIER_CIE10             (0x00000400)#define MCF_ETPU_ECIER_CIE11             (0x00000800)#define MCF_ETPU_ECIER_CIE12             (0x00001000)#define MCF_ETPU_ECIER_CIE13             (0x00002000)#define MCF_ETPU_ECIER_CIE14             (0x00004000)#define MCF_ETPU_ECIER_CIE15             (0x00008000)#define MCF_ETPU_ECIER_CIE16             (0x00010000)#define MCF_ETPU_ECIER_CIE17             (0x00020000)#define MCF_ETPU_ECIER_CIE18             (0x00040000)#define MCF_ETPU_ECIER_CIE19             (0x00080000)#define MCF_ETPU_ECIER_CIE20             (0x00100000)#define MCF_ETPU_ECIER_CIE21             (0x00200000)#define MCF_ETPU_ECIER_CIE22             (0x00400000)#define MCF_ETPU_ECIER_CIE23             (0x00800000)#define MCF_ETPU_ECIER_CIE24             (0x01000000)#define MCF_ETPU_ECIER_CIE25             (0x02000000)#define MCF_ETPU_ECIER_CIE26             (0x04000000)#define MCF_ETPU_ECIER_CIE27             (0x08000000)#define MCF_ETPU_ECIER_CIE28             (0x10000000)#define MCF_ETPU_ECIER_CIE29             (0x20000000)#define MCF_ETPU_ECIER_CIE30             (0x40000000)#define MCF_ETPU_ECIER_CIE31             (0x80000000)/* Bit definitions and macros for MCF_ETPU_ECDTRER */#define MCF_ETPU_ECDTRER_DTRE0           (0x00000001)#define MCF_ETPU_ECDTRER_DTRE1           (0x00000002)#define MCF_ETPU_ECDTRER_DTRE2           (0x00000004)#define MCF_ETPU_ECDTRER_DTRE3           (0x00000008)#define MCF_ETPU_ECDTRER_DTRE4           (0x00000010)#define MCF_ETPU_ECDTRER_DTRE5           (0x00000020)#define MCF_ETPU_ECDTRER_DTRE6           (0x00000040)#define MCF_ETPU_ECDTRER_DTRE7           (0x00000080)#define MCF_ETPU_ECDTRER_DTRE8           (0x00000100)#define MCF_ETPU_ECDTRER_DTRE9           (0x00000200)#define MCF_ETPU_ECDTRER_DTRE10          (0x00000400)#define MCF_ETPU_ECDTRER_DTRE11          (0x00000800)#define MCF_ETPU_ECDTRER_DTRE12          (0x00001000)#define MCF_ETPU_ECDTRER_DTRE13          (0x00002000)#define MCF_ETPU_ECDTRER_DTRE14          (0x00004000)#define MCF_ETPU_ECDTRER_DTRE15          (0x00008000)#define MCF_ETPU_ECDTRER_DTRE16          (0x00010000)#define MCF_ETPU_ECDTRER_DTRE17          (0x00020000)#define MCF_ETPU_ECDTRER_DTRE18          (0x00040000)#define MCF_ETPU_ECDTRER_DTRE19          (0x00080000)#define MCF_ETPU_ECDTRER_DTRE20          (0x00100000)#define MCF_ETPU_ECDTRER_DTRE21          (0x00200000)#define MCF_ETPU_ECDTRER_DTRE22          (0x00400000)#define MCF_ETPU_ECDTRER_DTRE23          (0x00800000)#define MCF_ETPU_ECDTRER_DTRE24          (0x01000000)#define MCF_ETPU_ECDTRER_DTRE25          (0x02000000)#define MCF_ETPU_ECDTRER_DTRE26          (0x04000000)#define MCF_ETPU_ECDTRER_DTRE27          (0x08000000)#define MCF_ETPU_ECDTRER_DTRE28          (0x10000000)#define MCF_ETPU_ECDTRER_DTRE29          (0x20000000)#define MCF_ETPU_ECDTRER_DTRE30          (0x40000000)#define MCF_ETPU_ECDTRER_DTRE31          (0x80000000)/* Bit definitions and macros for MCF_ETPU_ECPSSR */#define MCF_ETPU_ECPSSR_SR0              (0x00000001)#define MCF_ETPU_ECPSSR_SR1              (0x00000002)#define MCF_ETPU_ECPSSR_SR2              (0x00000004)#define MCF_ETPU_ECPSSR_SR3              (0x00000008)#define MCF_ETPU_ECPSSR_SR4              (0x00000010)#define MCF_ETPU_ECPSSR_SR5              (0x00000020)#define MCF_ETPU_ECPSSR_SR6              (0x00000040)#define MCF_ETPU_ECPSSR_SR7              (0x00000080)#define MCF_ETPU_ECPSSR_SR8              (0x00000100)#define MCF_ETPU_ECPSSR_SR9              (0x00000200)#define MCF_ETPU_ECPSSR_SR10             (0x00000400)#define MCF_ETPU_ECPSSR_SR11             (0x00000800)#define MCF_ETPU_ECPSSR_SR12             (0x00001000)#define MCF_ETPU_ECPSSR_SR13             (0x00002000)#define MCF_ETPU_ECPSSR_SR14             (0x00004000)#define MCF_ETPU_ECPSSR_SR15             (0x00008000)#define MCF_ETPU_ECPSSR_SR16             (0x00010000)#define MCF_ETPU_ECPSSR_SR17             (0x00020000)#define MCF_ETPU_ECPSSR_SR18             (0x00040000)#define MCF_ETPU_ECPSSR_SR19             (0x00080000)#define MCF_ETPU_ECPSSR_SR20             (0x00100000)#define MCF_ETPU_ECPSSR_SR21             (0x00200000)#define MCF_ETPU_ECPSSR_SR22             (0x00400000)#define MCF_ETPU_ECPSSR_SR23             (0x00800000)#define MCF_ETPU_ECPSSR_SR24             (0x01000000)#define MCF_ETPU_ECPSSR_SR25             (0x02000000)#define MCF_ETPU_ECPSSR_SR26             (0x04000000)#define MCF_ETPU_ECPSSR_SR27             (0x08000000)#define MCF_ETPU_ECPSSR_SR28             (0x10000000)#define MCF_ETPU_ECPSSR_SR29             (0x20000000)#define MCF_ETPU_ECPSSR_SR30             (0x40000000)#define MCF_ETPU_ECPSSR_SR31             (0x80000000)/* Bit definitions and macros for MCF_ETPU_ECSSR */#define MCF_ETPU_ECSSR_SS0               (0x00000001)#define MCF_ETPU_ECSSR_SS1               (0x00000002)#define MCF_ETPU_ECSSR_SS2               (0x00000004)#define MCF_ETPU_ECSSR_SS3               (0x00000008)#define MCF_ETPU_ECSSR_SS4               (0x00000010)#define MCF_ETPU_ECSSR_SS5               (0x00000020)#define MCF_ETPU_ECSSR_SS6               (0x00000040)#define MCF_ETPU_ECSSR_SS7               (0x00000080)#define MCF_ETPU_ECSSR_SS8               (0x00000100)#define MCF_ETPU_ECSSR_SS9               (0x00000200)#define MCF_ETPU_ECSSR_SS10              (0x00000400)#define MCF_ETPU_ECSSR_SS11              (0x00000800)#define MCF_ETPU_ECSSR_SS12              (0x00001000)#define MCF_ETPU_ECSSR_SS13              (0x00002000)#define MCF_ETPU_ECSSR_SS14              (0x00004000)#define MCF_ETPU_ECSSR_SS15              (0x00008000)#define MCF_ETPU_ECSSR_SS16              (0x00010000)#define MCF_ETPU_ECSSR_SS17              (0x00020000)#define MCF_ETPU_ECSSR_SS18              (0x00040000)#define MCF_ETPU_ECSSR_SS19              (0x00080000)#define MCF_ETPU_ECSSR_SS20              (0x00100000)#define MCF_ETPU_ECSSR_SS21              (0x00200000)#define MCF_ETPU_ECSSR_SS22              (0x00400000)#define MCF_ETPU_ECSSR_SS23              (0x00800000)#define MCF_ETPU_ECSSR_SS24              (0x01000000)#define MCF_ETPU_ECSSR_SS25              (0x02000000)#define MCF_ETPU_ECSSR_SS26              (0x04000000)#define MCF_ETPU_ECSSR_SS27              (0x08000000)#define MCF_ETPU_ECSSR_SS28              (0x10000000)#define MCF_ETPU_ECSSR_SS29              (0x20000000)#define MCF_ETPU_ECSSR_SS30              (0x40000000)#define MCF_ETPU_ECSSR_SS31              (0x80000000)/* Bit definitions and macros for MCF_ETPU_ECnSCR */#define MCF_ETPU_ECnSCR_FM(x)            (((x)&0x00000003)<<0)#define MCF_ETPU_ECnSCR_OBE              (0x00002000)#define MCF_ETPU_ECnSCR_OPS              (0x00004000)#define MCF_ETPU_ECnSCR_IPS              (0x00008000)#define MCF_ETPU_ECnSCR_DTROS            (0x00400000)#define MCF_ETPU_ECnSCR_DTRS             (0x00800000)#define MCF_ETPU_ECnSCR_CIOS             (0x40000000)#define MCF_ETPU_ECnSCR_CIS              (0x80000000)/* Bit definitions and macros for MCF_ETPU_ECnCR */#define MCF_ETPU_ECnCR_CPBA(x)           (((x)&0x000007FF)<<0)#define MCF_ETPU_ECnCR_OPOL              (0x00004000)#define MCF_ETPU_ECnCR_ODIS              (0x00008000)#define MCF_ETPU_ECnCR_CFS(x)            (((x)&0x0000001F)<<16)#define MCF_ETPU_ECnCR_ETCS              (0x01000000)#define MCF_ETPU_ECnCR_CPR(x)            (((x)&0x00000003)<<28)#define MCF_ETPU_ECnCR_DTRE              (0x40000000)#define MCF_ETPU_ECnCR_CIE               (0x80000000)/* Bit definitions and macros for MCF_ETPU_ECnHSSR */#define MCF_ETPU_ECnHSSR_HSR(x)          (((x)&0x00000007)<<0)/********************************************************************/#endif /* __MCF523X_ETPU_H__ */
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