tgcs_cpld.txt

实现8通道模拟/数字转换和数字/模拟转换的例子,采用ISA总线控制逻辑.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package TGCS_CPLD is
--------------------------------------------------------------------------------
component HC245_8
port(
         A, B : inout std_logic_vector(7 downto 0);
         DIR, GBAR : in std_logic);
end component;
---------------------------------------------------------------------------------
component D2_4E
port(
            A0, A1, G : in std_logic;
            Y0,Y1, Y2, Y3 : out std_logic);
end component;
-------------------------------------------------------------------------------
component HC273_3
port(
          clr,clk:in std_logic;
          D:in std_logic_vector(2 downto 0);
		    Q:out std_logic_vector(2 downto 0)
		 );
end component;
--------------------------------------------------------------------
component HC273_8
port(
          clr,clk:in std_logic;
          D:in std_logic_vector(7 downto 0);
		    Q:out std_logic_vector(7 downto 0)
		 );
end component;
---------------------------------------------------------------------------
component COMP5
port(
          nG:in std_logic;
          EQ:out std_logic;
		    P,Q:IN STD_LOGIC_VECTOR(6 downto 1)
		);
end component;
---------------------------------------------------------------
component D9BC
port(
       A,B:IN STD_LOGIC;
       AB:OUT STD_LOGIC
	 );
end component;
-------------------------------------------------------------------
end TGCS_CPLD;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.TGCS_CPLD.ALL;

entity TGCS is
port(
SD:inout std_logic_vector(7 downto 0);
D:inout std_logic_vector(7 downto 0);
A:inout std_logic_vector(2 downto 0);
SA:in std_logic_vector(9 downto 0);
Status,nIOR,nIOW,RESDRV,AEN:in std_logic;
nLDAC,nADC,nDAC1,nDAC2:out std_logic;
REL:out std_logic_vector(7 downto 0);
CHN:out std_logic_vector(2 downto 0);
NRES,nWR:inout std_logic
);

end TGCS;

architecture Behavioral of TGCS is

signal nnMUX,RES,nSTAT,nMUX,nRE1,RE1,nRD,Y2,Y3,EQ,G:std_logic;
signal P,Q:std_logic_vector(6 downto 1);
begin
-----------------------------------------------------   
D1:HC245_8 port map(SD,D,nRD,EQ);
D2:HC273_3 port map(nRES,nnMUX,D(2 downto 0),CHN);
D3:COMP5 port map(G,EQ,P,Q);
D5:HC273_8 port map(nRES,nRE1,D,REL);
D8B:D2_4E port map(SA(1),SA(2),Y2,nADC,nMUX,nSTAT,RE1);
D8A:D2_4E port map(SA(3),SA(4),EQ,nDAC1,nDAC2,Y2,Y3);
D9:D9BC port map(nWR,nRD,G);
------------------------------------------------------
P<=AEN&SA(9)&SA(8)&SA(7)&SA(6)&SA(5);
Q<="011000";
nLDAC<='0';
nRES<=not RES;
nnMUX<=not nMUX;
nRE1<=not RE1;
A(2 downto 0)<=SA(2 downto 0);
nRD<=nIOR;
nWR<=nIOW;
RES<=RESDRV;
---------------------------------------
D(2 downto 0)<="101" when nSTAT<='0' else "ZZZ";
------------------------------------------------------------
end architecture Behavioral;