📄 read_reg.h
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/*ubicmn.h*/
#define U8 unsigned char
#define U16 unsigned
#define U32 int
#define S8 char
#define S16 short
#define S32 long
#define XD xdata
#define XD2 xdata
#define XC code
#define GP
#define MAX_U16 65535
#define MAX_S16 32767
#ifndef IN
#define IN
#endif
#ifndef OUT
#define OUT
#endif
#ifndef INOUT
#define INOUT
#endif
#define MIN(a,b) (((a)<=(b))?(a):(b))
#define MAX(a,b) (((a)<=(b))?(b):(a))
#define UMO_WAIT_USB_PKT_TICKS 66667 //initial value for "gWaitPktTicks"
//this value must be measured from "DEV_TEST_4_GetWaitPacketTicks(200)"
// 66667 : RISC_sleep_nsec(1000);
//7.28
//-------------------------------------------------------------------------------
// Initialization State
//-------------------------------------------------------------------------------
#define IS_NO_INIT 0 //not initilized
#define IS_ENUM_OK 1 //passed enumeration
#define IS_FILESYS_OK 2 //passed file system initialization
sbit MCU_A0=P3^4;
sbit MCU_CS=P3^5;
sbit MCU_WR=P3^6;
sbit MCU_RD=P3^7;
sbit MCU_INTRQ=P3^2;
sbit USB_RESET=P3^1;
sbit MCU_SEL_OUT=P3^0;
#define IO_IRQ_READY MCU_INTRQ=0
#define IO_IRQ_PENDING MCU_INTRQ=1
#define IO_PLUGIN_READY MCU_SEL_OUT=0
#define IO_PLUGIN_DET MCU_SEL_OUT=1
#define IO_USB_RET_HIGH USB_RESET=0
#define IO_USB_RET_LOW USB_RESET=1
#define IO_BUS_RESET_HIGH USB_RESET=1
#define IO_BUS_RESET_LOW USB_RESET=0
//_________ UBi9021 Chip Reset ____________
#define PW_RST_PORT_DIR_OUT
#define PW_RST_PORT_LOW {usb_reset(1);}while(0)
#define PW_RST_PORT_HIGH {usb_reset(0);}while(0)
//_________ io control ___________________
#define UBi9021_IRQ_PENDING() usb_irq_poll()
#define UH_DEV_IS_PLUGGEDIN() usb_plugin()
//_________ io control ___________________
//_________ USB Mass Storage Options _____
//#define WFIRQ_SLEEP_TIME 10000 //RISC_sleep_nsec(10000);
#define WFIRQ_SLEEP_TIME 1000 //RISC_sleep_nsec(1000);
#define UMO_RESET_IDLE_TICKS 1000 //4u-sec //make sure that the reset pulse low enough
#define UMO_ENABLE_READCAPACITY 0 //1:enable read-capacity when enumeration, default=0
#define UMO_ENABLE_MULTI_LUN 1 //default=0
#define UMO_DEFAULT_HUB_ADDRESS 4 //default=4
#define UMO_DEFAULT_DEV_ADDRESS 5 //default=5
#define UMO_INIT_FAIL_DEV_ADDRESS 6 //init failed device
#define UMO_DEVICE_INIT_OK 0x5A
#define UH_ENFORCE_HOST_MODE() DEV_WriteReg(RD_CHIP_CTR,0x40)//DEV_WriteReg(RD_CHIP_CTR,0xF0)
//-------------------------------------------------------------------------------
// USB Host Irq
//-------------------------------------------------------------------------------
#define UH_IRQ_USB_PKT_DONE (0x01)
#define UH_IRQ_SOF (0x02)
#define UH_IRQ_FAKE_STALL (0x04) //not a real irq
#define UH_IRQ_READ_READY (0x10)
#define UH_IRQ_WRITE_READY (0x20)
#define UH_IRQ_AUTO_ENUM_DONE (0x40)
#define IO_IRQ_READY MCU_INTRQ=0
#define IO_IRQ_PENDING MCU_INTRQ=1
#define IO_PLUGIN_READY MCU_SEL_OUT=0
#define IO_PLUGIN_DET MCU_SEL_OUT=1
#define IO_USB_RET_HIGH USB_RESET=0
#define IO_USB_RET_LOW USB_RESET=1
#define IO_BUS_RESET_HIGH USB_RESET=1
#define IO_BUS_RESET_LOW USB_RESET=0
//transfer target
#define TxNULL ((U8 GP*)0)//((U8 GP*)-2)
#define TxCODEC ((U8 GP*)1)//((U8 GP*)-1)
/*ubi51.h*/
#define RH_USB_HOST_BASE_ADDR ((U8)0x0B)
#define RH_USB_HOST_BASE_LEN ((U8)0x01)
#define RH_EP_ADDR_N_PID ((U8)0x02)
#define RH_LAST_PKT_STS ((U8)0x03)
#define RH_DEV_ADDR ((U8)0x04)
#define RH_CHIP_CTR1 ((U8)0x05)
#define RH_CHIP_CTR2 ((U8)0x06)
#define RH_INT_EN ((U8)0x07)
#define RH_INT_STS ((U8)0x08)
#define RH_FIFO_SZ_LO ((U8)0x0C)
#define RH_FIFO_SZ_HI ((U8)0x0D)
#define RH_INT_EP_ADDR ((U8)0x0E)
#define RH_INT_TIME ((U8)0x0F)
#define RH_RNDM_READ_LSB ((U8)0x11)
#define RH_RNDM_READ_MSB ((U8)0x12)
//registers for host mode: short CBW
#define RH_MASS_ADDR1 ((U8)0x13)
#define RH_MASS_ADDR2 ((U8)0x14)
#define RH_MASS_ADDR3 ((U8)0x15)
#define RH_MASS_ADDR4 ((U8)0x16)
#define RH_MASS_SZ ((U8)0x17)
#define RH_MASS_CTR ((U8)0x18)
//registers for device
#define RD_CHIP_CTR ((U8)0x19)
#define RD_HOST_EP_ADDR ((U8)0x1A)
#define RD_INT_STS ((U8)0x1B)
#define RD_INT_EN ((U8)0x1C)
#define RD_DESC_SIZE ((U8)0x1E) //descriptor size to send
#define RD_ROM_INDEX ((U8)0x1D) //kind of descriptor
#define RD_FIFO_SZ_LO RH_FIFO_SZ_LO
#define RD_FIFO_SZ_HI RH_FIFO_SZ_HI
//-------------------------------------------------------------------------------
// ERROR Codes
//-------------------------------------------------------------------------------
#define RES_OK 0x00
#define RES_ERR 0x80
#define RES_ERR_FAT_LOST_CLUS 0x81
#define RES_ERR_TESTUNIT 0x82 //timeout for testunitready
#define RES_ERR_NO_SECTOR 0x83 //error for sector access
#define RES_ERR_FTLINIT 0x84 //failed to initialize FTL
#define RES_ERR_FATINIT 0x85 //failed to initialize FAT
#define RES_ERR_EOC 0x86 //End Of Cluster (No more cluster)
#define RES_ERR_SCSI_CBW 0x87 //CBW packet error
#define RES_ERR_SCSI_DATA 0x88 //DATA In or Out error
#define RES_ERR_SCSI_CSW 0x89 //CSW status error
#define RES_ERR_SCSI_CMD_IGNORED 0x8A
#define RES_ERR_USB_TIMEOUT 0x8B
//-------------------------------------------------------------------------------
// UBi9021 Control Macros
//-------------------------------------------------------------------------------
#define UH_FIFO_ROLLBACK_OUT() DEV_WriteReg(RH_CHIP_CTR2,(U8)0x18)
#define UH_FIFO_ROLLBACK_IN() DEV_WriteReg(RH_CHIP_CTR2,(U8)0x19)
#define UH_FIFO_DIR_OUT() DEV_WriteReg(RH_CHIP_CTR2,(U8)0x10)
#define UH_FIFO_DIR_IN() DEV_WriteReg(RH_CHIP_CTR2,(U8)0x11)
#define UH_SOF_EN_FIFO_DIR_OUT() UH_FIFO_DIR_OUT()
#define UH_SOF_EN_FIFO_DIR_IN() UH_FIFO_DIR_IN()
#define UH_SOF_DIS() DEV_WriteReg(RH_CHIP_CTR2,(U8)0x00)
#define UH_SET_FIFO_SZ(wBytCnt) \
DEV_WriteReg(RH_FIFO_SZ_LO,(U8)(wBytCnt)),\
DEV_WriteReg(RH_FIFO_SZ_HI,(U8)((wBytCnt)>>8))
#define UH_SET_FIFO_SZ_EACH(hi,lo) \
DEV_WriteReg(RH_FIFO_SZ_LO,(lo)),\
DEV_WriteReg(RH_FIFO_SZ_HI,(hi))
#define UH_RNDM_READ_START(wBytOff) \
DEV_WriteReg(RH_RNDM_READ_LSB,(U8)(wBytOff)),\
DEV_WriteReg(RH_RNDM_READ_MSB,(0x80|(U8)((wBytOff)>>8)))
#define UH_RNDM_READ_END() \
DEV_WriteReg(RH_RNDM_READ_LSB,0),\
DEV_WriteReg(RH_RNDM_READ_MSB,0),\
UH_FIFO_ROLLBACK_IN()//UH_FIFO_ROLLBACK_OUT()
//#define UH_IRQ_EN(bIRQ) gIrqEn=((bIRQ)|UH_IRQ_SOF)
#define UH_IRQ_EN(bIRQ) gIrqEn=(bIRQ)
//gIrqEn=(UH_IRQ_SOF|UH_IRQ_USB_PKT_DONE|bIRQ)
//DEV_WriteReg(RH_INT_EN,(UH_IRQ_USB_PKT_DONE|bIRQ))
//DEV_WriteReg(RH_INT_EN,(UH_IRQ_SOF|bIRQ))
//DEV_WriteReg(RH_INT_EN,(UH_IRQ_SOF|UH_IRQ_USB_PKT_DONE|bIRQ))
#define UH_ENFORCE_HOST_MODE() DEV_WriteReg(RD_CHIP_CTR,0x40)//DEV_WriteReg(RD_CHIP_CTR,0xF0)
#define UH_Trigger(ep) DEV_WriteReg(RH_INT_EN,gIrqEn),DEV_WriteReg(RH_EP_ADDR_N_PID,(gEP=(ep)))
///#define UH_Trigger(ep) DEV_WriteReg(RH_INT_EN,gIrqEn),DEV_ReadReg(RH_INT_STS),DEV_WriteReg(RH_EP_ADDR_N_PID,gEP=(ep))
#define USB_VER_UNKNOWN 0
#define USB_VER_1X 1
#define USB_VER_2X 2
//-------------------------------------------------------------------------------
// UBi9021 Reset mode
//-------------------------------------------------------------------------------
#define RST9021_NORMAL_RESET 0 //using register command
#define RST9021_FULL_RESET 1 //using reset pin
#define RST9021_RESTORE 2 //restore previous settings (Device-Address,SOF,FIFO-Direction,
//-------------------------------------------------------------------------------
// USB Host Last Packet Status
//-------------------------------------------------------------------------------
#define UH_LST_PKT_STS_ACK (1<<0)
#define UH_LST_PKT_STS_ERR (1<<1)
#define UH_LST_PKT_STS_TIMEOUT (1<<2)
#define UH_LST_PKT_STS_SEQ (1<<3)
#define UH_LST_PKT_STS_NAK (1<<4)
#define UH_LST_PKT_STS_STALL (1<<5)
#define WFIRQ_SLEEP_TIME 1000 //RISC_sleep_nsec(1000);
/******************************************************************************
* USB SETUP TRANSFER
******************************************************************************/
#define USB_SETUP_GET_DEV_DESC_INIT 0 //len
#define USB_SETUP_GET_DEV_DESC 1 //len
#define USB_SETUP_GET_CFG_DESC 2 //len
#define USB_SETUP_SET_ADDR 3 //addr
#define USB_SETUP_SET_CFG 4 //cfg
#define USB_SETUP_SET_PORT_PWR 5
#define USB_SETUP_PORT_RST 6
#define USB_SETUP_CLR_PORT_RST 7
#define USB_SETUP_GET_PORT_STS 8
#define USB_SETUP_GET_MAX_LUN 9
#define gWaitUsbPktMsec gWaitPktTicks
U8 USB_ControlTransfer(U8 type, U8 arg, U8* buf);
void MemFill(U8* buf, U8 val, U16 bytCnt);
void DEV_WriteRegMulti(U8 reg, U16 cnt, U8* buf);
U8 DEV_ReadRegMulti(U8 reg, U16 cnt, register U8* buf);
U8 DEV_WaitForIrq(U8 bIRQ);
U8 DEV_SafeTriggerAndWaitForInPacket(U8 ep, U16 bytCnt, U16 msec);
void DEV_WriteReg(U8 addr,U8 dat);
U8 DEV_ReadReg(U8 addr);
U8 DEV_ResetChip(U8 mode);
U8 USB_ResetPipe(U8 ep);
void RISC_sleep_cycles(int n);
U8 DEV_WaitMS(U16 msec);
#define GET_UBi9021_IRQ_STS(usbIrq) usbIrq=DEV_ReadReg(RH_INT_STS)
#define ISOK(res) ((res)<RES_ERR)
#define ISERR(res) ((res)>=RES_ERR)
#define ISERR32(a) (a>=(U32)0x80000000)
//-------------------------------------------------------------------------------
// USB Interface
//-------------------------------------------------------------------------------
#define DESC_CONFIG ((U8)0x02)
#define DESC_INTERFACE ((U8)0x04)
#define DESC_ENDPOINT ((U8)0x05)
#define IFC_MASSSTORAGE ((U8)0x08)
#define IFC_IMAGING ((U8)0x06)
#define IFP_BULKONLY ((U8)0x50)
#define IFP_CBI ((U8)0x01)
#define EPTYPE_BULK ((U8)0x02)
#define nOK08 ((U8)0xFF)
#define nOK16 ((U16)0xFFFF)
#define nOK32 ((U32)0xFFFFFFFF)
#define UH_IRQ_SEND_READ_WRITE_CMD UH_IRQ_WRITE_READY⌨️ 快捷键说明
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