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📄 forney_conv12x17.vhd

📁 一种交织算法——forney交织
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					END IF;
					IF(SIGNAL_BIT8='1'OR SIGNAL_BIT11='1')THEN 
						SIGNAL_BIT15<=SIGNAL_BIT14;
						SIGNAL_BIT14<=SIGNAL_ND;		--SIGNAL_BIT5都是来自下一个进程REG_INPUTS
					END IF;
				END IF;
			END IF;
		END IF;
	END PROCESS;
VFD_R_PROC:PROCESS(SIGNAL_FD,SIGNAL_ND)		   --SIGNAL_FD,SIGNAL_BIT5都是来自下一个进程REG_INPUTS
	BEGIN 
		SIGNAL_BIT11<=(SIGNAL_FD AND SIGNAL_ND);   --SIGNAL_ND<=ND,SIGNAL_FD<=FD ,ND和FD同时为1时,SIGNAL_BIT11=1
	END PROCESS;
REG_INPUTS:PROCESS(CLK,ND,FD,DIN,SIGNAL_RFFD,SIGNAL_BIT9)
	BEGIN 
		IF C_PIPE_LEVEL/=INT33 THEN    --该语句不执行
			IF CLK'event AND CLK='1'THEN 
				IF SIGNAL_CE='1'THEN 
					IF SIGNAL_SCLR='1'THEN 	 
						SIGNAL_ND<='0';
						SIGNAL_FD<='0';
						SIGNAL_BIT7<='0';
						SIGNAL_DIN<=(OTHERS=>'0');
						SIGNAL_BIT8<='0';
					ELSE 
						SIGNAL_ND<=ND;
						SIGNAL_FD<=FD;
						SIGNAL_BIT7<=SIGNAL_RFFD;
						SIGNAL_DIN<=DIN;
						SIGNAL_BIT8<=SIGNAL_BIT9;
					END IF;
				END IF;
			END IF;
		ELSE 
			SIGNAL_ND<=ND;	   --将输入ND信号送入寄存器SIGNAL_BIT5
			SIGNAL_FD<=FD;	   --将输入FD信号送入寄存器SIGNAL_BIT6
			SIGNAL_DIN<=DIN;	   --将输入数据送入寄存器SIGNAL_VECTOR
			SIGNAL_BIT7<=SIGNAL_RFFD;  --SIGNAL_RFFD是来自进程RFFD_INT_PROC的信号
			SIGNAL_BIT8<=SIGNAL_BIT9;  --SIGNAL_BIT9是来自下下一个进程FD_RX的信号
		END IF;
	END PROCESS;
RFFD_INT_PROC:PROCESS(SIGNAL_VECTOR1(0))		  --SIGNAL_VECTOR1(0)是来自进程SWITCH_POSN的信号
	BEGIN 
		SIGNAL_RFFD<=SIGNAL_VECTOR1(0);--SIGNAL_RFFD是作为该进程与进程OPTIONAL_RFFD通信的信号
	END PROCESS;
SWITCH_POSN:PROCESS(CLK)	--SIGNAL_ACLR是来自进程ACLR_PROC的信号
		PROCEDURE PROCEDURE1 IS 		  --该过程实现将分之切换到第0分支
		BEGIN 
			FOR I IN 0 TO C_NUM_BRANCHES-1 LOOP 
				SIGNAL_VECTOR1(I)<='0';
			END LOOP;
			SIGNAL_VECTOR1(0)<='1';
		END;

		PROCEDURE PROCEDURE2 IS 
		BEGIN 
			FOR I IN 0 TO C_NUM_BRANCHES-1 LOOP 
				SIGNAL_VECTOR1(I)<='0';
			END LOOP;
			SIGNAL_VECTOR1(1)<='1';
		END;

		PROCEDURE PROCEDURE3 IS 			  --该过程实现将SIGNAL_VECTOR1(0 TO 11)进行右移操作
		BEGIN 
			FOR I IN 1 TO C_NUM_BRANCHES-1 LOOP 
				SIGNAL_VECTOR1(I)<=SIGNAL_VECTOR1(I-1);
			END LOOP;
			SIGNAL_VECTOR1(0)<=SIGNAL_VECTOR1(C_NUM_BRANCHES-1);
		END;
	BEGIN 
		IF CLK'event AND CLK='1'THEN 
			IF SIGNAL_CE='1'THEN 
				IF SIGNAL_SCLR='1'THEN 
					PROCEDURE1;
				ELSIF(FD='1'AND ND='1'AND SIGNAL_BIT9='0')THEN 	  --SIGNAL_BIT9是来自下下一个进程FD_RX的信号
					PROCEDURE2;
				ELSIF(FD='1'AND ND='1'AND SIGNAL_RFFD='0')THEN 
					PROCEDURE2;
				ELSIF ND='1'AND SIGNAL_BIT9='1'THEN 
					PROCEDURE3;
				END IF;
			END IF;
		END IF;
	END PROCESS;

SHIFTBR:PROCESS(CLK)		 --SIGNAL_ACLR是来自进程ACLR_PROC的信号
		PROCEDURE PROCEDURE1 IS 
		BEGIN 
			FOR I IN 0 TO C_NUM_BRANCHES-1 LOOP 
				SIGNAL_VECTOR2(I)<='0';
			END LOOP;
		END;
		PROCEDURE PROCEDURE2 IS 
		BEGIN 
			FOR I IN 0 TO C_NUM_BRANCHES-1 LOOP 
				SIGNAL_VECTOR2(I)<='0';
			END LOOP;
			SIGNAL_VECTOR2(0)<='1';
		END;
		PROCEDURE PROCEDURE3 IS 	   --功能待测试
		BEGIN 
			FOR I IN 1 TO C_NUM_BRANCHES-1 LOOP 
				SIGNAL_VECTOR2(I)<=SIGNAL_VECTOR2(I-1);
			END LOOP;
			SIGNAL_VECTOR2(0)<=SIGNAL_VECTOR2(C_NUM_BRANCHES-1);
		END;
	BEGIN 
		IF CLK'event AND CLK='1'THEN 
			IF SIGNAL_CE='1'THEN 
				IF SIGNAL_SCLR='1'THEN 
					PROCEDURE1;
					SIGNAL_RECORD1.DATA<=(OTHERS=>'X');
				ELSIF SIGNAL_ND='1'THEN 
					IF SIGNAL_BIT11='1'THEN 
						PROCEDURE2;
					ELSIF SIGNAL_BIT8='1'THEN 
						PROCEDURE3;
					END IF;
					SIGNAL_RECORD1.DATA<=SIGNAL_DIN;	 --输入数据缓冲寄存器将输入数据送给SIGNAL_RECORD1.DATA
				END IF;
			END IF;
		END IF;
	END PROCESS;
FD_RX:  PROCESS(CLK)		   --SIGNAL_ACLR是来自进程ACLR_PROC的信号
	BEGIN 
		IF(CLK'event AND CLK='1')THEN 
			IF SIGNAL_CE='1'THEN
 				IF SIGNAL_SCLR='1'THEN 
 					SIGNAL_BIT9<='0';
 				ELSIF FD='1'AND ND='1'THEN 
 					SIGNAL_BIT9<='1';
 				END IF;
 			END IF;
 		END IF;
 	END PROCESS;

CE_PROC:PROCESS(CE)
	BEGIN 
		IF C_HAS_CE/=0 THEN 
			SIGNAL_CE<=CE;
		ELSE 
			SIGNAL_CE<='1';
		END IF;
	END PROCESS;
SCLR_PROC:PROCESS(SCLR)
	BEGIN 
		IF C_HAS_SCLR/=0 THEN 
			SIGNAL_SCLR<=SCLR;
		ELSE 
			SIGNAL_SCLR<='0';
		END IF;
	END PROCESS;
SYNC_PROC:PROCESS(SIGNAL_BIT11,SIGNAL_BIT7)	--SIGNAL_BIT7是来自进程REG_INPUTS的信号,SIGNAL_BIT11是来自进程VFD_R_PROC的信号
	BEGIN 
		SIGNAL_BIT12<=SIGNAL_BIT11 AND NOT SIGNAL_BIT7;		--SIGNAL_BIT7<=SIGNAL_RFFD;  --SIGNAL_RFFD是来自进程RFFD_INT_PROC的信号
	END PROCESS;

RDYPORT:PROCESS(SIGNAL_BIT20,SIGNAL_BIT22)	 ----SIGNAL_BIT20是来自进程NDO_DELAY_PROC的信号,SIGNAL_BIT22是来自进程RDY_ENABLE_PROC的信号
	BEGIN 
		SIGNAL_BIT23<=SIGNAL_BIT20 AND(SIGNAL_BIT22);
	END PROCESS;
FDO_PROC:PROCESS(CLK)
	BEGIN 
		IF(CLK'event AND CLK='1')THEN 
			IF SIGNAL_CE='1'THEN 
				IF SIGNAL_SCLR='1'THEN 
					SIGNAL_VECTOR7<=(OTHERS=>'0');
					SIGNAL_BIT21<='0';
				ELSE 
					IF CON_INTEGER1>1 THEN 
						IF SIGNAL_BIT16='1'THEN 	  --SIGNAL_BIT16是来自进程DELSIGS的信号
							SIGNAL_VECTOR7(0)<=SIGNAL_BIT19;
							FOR I IN 1 TO(CON_INTEGER1)LOOP 
								SIGNAL_VECTOR7(I)<=SIGNAL_VECTOR7(I-1);
								SIGNAL_BIT21<=SIGNAL_VECTOR7(I-1);
							END LOOP;
						END IF;
						IF SIGNAL_BIT13='1'THEN 	--SIGNAL_BIT13是来自进程SYNC_0_PROC的信号
							SIGNAL_VECTOR7<=(OTHERS=>'0');
							SIGNAL_BIT21<='0';
						END IF;
					ELSE 
						IF SIGNAL_BIT13='1'THEN 	--SIGNAL_BIT13是来自进程SYNC_0_PROC的信号
							SIGNAL_BIT21<='0';
						ELSIF SIGNAL_BIT16='1'THEN 	--SIGNAL_BIT16是来自进程DELSIGS的信号
							SIGNAL_BIT21<=SIGNAL_BIT19;
						END IF;
					END IF;
				END IF;
			END IF;
		END IF;
	END PROCESS;
RDY_ENABLE_PROC:PROCESS(CLK)
	BEGIN 
		IF(CLK'event AND CLK='1')THEN 
			IF SIGNAL_CE='1'THEN
 				IF SIGNAL_SCLR='1'THEN 
 					SIGNAL_VECTOR8<=(OTHERS=>'0');
 					SIGNAL_BIT22<='0';
 				ELSE 
 					IF CON_INTEGER1>1 THEN 
 						IF SIGNAL_BIT16='1'THEN 	   --SIGNAL_BIT16是来自进程DELSIGS的信号
 							IF SIGNAL_BIT19='1'THEN 
 								SIGNAL_VECTOR8(0)<='1';
 							END IF;
 							FOR I IN 1 TO(CON_INTEGER1)LOOP 
 								SIGNAL_VECTOR8(I)<=SIGNAL_VECTOR8(I-1);
 								SIGNAL_BIT22<=SIGNAL_VECTOR8(I-1);
							END LOOP;
						END IF;
						IF SIGNAL_BIT13='1'THEN 		--SIGNAL_BIT13是来自进程SYNC_0_PROC的信号
							SIGNAL_VECTOR8<=(OTHERS=>'0');
							SIGNAL_BIT22<='0';
						END IF;
					ELSE 
						IF SIGNAL_BIT13='1'THEN 
							SIGNAL_BIT22<='0';
						ELSIF SIGNAL_BIT16='1'THEN 		 --SIGNAL_BIT16是来自进程DELSIGS的信号
							IF SIGNAL_BIT19='1'THEN 	 --SIGNAL_BIT19是来自进程DELSIGS的信号
								SIGNAL_BIT22<='1';
							END IF;
						END IF;
					END IF;
				END IF;
			END IF;
		END IF;
	END PROCESS;
SYNC_0_PROC:PROCESS(CLK)
	BEGIN 
		IF(CLK'event AND CLK='1')THEN 
			IF SIGNAL_CE='1'THEN 
				IF SIGNAL_SCLR='1'THEN 
					SIGNAL_BIT13<='0';
				ELSE 
					SIGNAL_BIT13<=SIGNAL_BIT12;			--SIGNAL_BIT12是来自进程SYNC_PROC的信号
				END IF;
			END IF;
		END IF;
	END PROCESS;
END BEHAVIORAL;	

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