rominit.s

MPC8260的vxworks BSP源码

/* romInit.s - Motorola ads8260 ROM initialization module  Note by wangyan: for v.2 */

/* Copyright 1984-1999 Wind River Systems, Inc. */
	.data
	.globl  copyright_wind_river
	.long   copyright_wind_river

/*
modification history
--------------------
01f,14mar00,ms_  add support for PILOT revision of board
01e,04mar00,ml   changes for board rev "PILOT" (SIUMCR.DPPC/L2CPC & PSDMR.BSMA)
01d,16sep99,ms_  get some .h files from h/drv instead of locally
01c,15jul99,ms_  make compliant with our coding standards
01b,20may99,cn   fixed include m8260Cpm.h
01a,19may99,cn   written from ads860/romInit.s, 01m.
*/

/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 8 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().

*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "cacheLib.h"
#include "config.h"
#include "regs.h"	
#include "sysLib.h"
#include "m8260Siu.h"
#include "drv/timer/m8260Clock.h"
#include "drv/mem/m8260Memc.h"
 
	/* internals */

	.globl	_romInit	/* start of system code */
	.globl	romInit		/* start of system code */
	
	/* externals */

	.extern romStart	/* system initialization routine */

	.text
  .fill   1,1,HRCW_BYTE_0     /* byte 0 (MSByte) of the configuration master's Hard Reset Configuration Word */
  .fill   7,1,0       /* Fill with 7 zeros */

 .fill   1,1,HRCW_BYTE_1   
 .fill   7,1,0
 
 .fill   1,1,HRCW_BYTE_2   
 .fill   7,1,0
 
 .fill   1,1,HRCW_BYTE_3    /* This is the LSByte */
 .fill   231,1,0     /* The rest of the space are filled with zeros */
	.align 2

/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
*
* romInit
*     (
*     int startType	/@ only used by 2nd entry point @/
*     )
*/

_romInit:
romInit:

        lis     r5, HIADJ (0Xf0000000)
        addi    r5, r5, LO (0Xf0000000)
	lis	r6, HIADJ (M8260_PDIRC (0x0f000000))	
	addi	r6, r6, LO (M8260_PDIRC (0x0f000000))
	stw	r5, 0 (r6)

        lis     r5, HIADJ (0Xa0000000)
        addi    r5, r5, LO (0Xa0000000)
	lis	r6, HIADJ (M8260_PDATC (0x0f000000))	
	addi	r6, r6, LO (M8260_PDATC (0x0f000000))
	stw	r5, 0 (r6)
       
        bl	cold		/* jump to the cold boot initialization */
	nop
	bl	start		/* jump to the warm boot initialization */

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii   "Copyright 1984-1999 Wind River Systems, Inc."
	.align 2

cold:

        li      r3, BOOT_COLD   /* set cold boot as start type */

	addis    r4,0,0x0F01    /* R4 holds the IMMR base address */

	addis    r5,0,0x0000    /* Clear out all mask bits */
        
    	ori      r5,r5,0x0856	 
	stw      r5,0x0104(r4)  /* option register for bank 0 */
	isync			/* synchronize */

	/*
	 * initialize the IMMR register before any non-core registers
	 * modification. The default IMMR base address was 0x0F000000,
	 * as originally programmed in the Hard Reset Configuration Word.
	 */
        
            

	lis	r4, HIADJ (INTERNAL_MEM_MAP_ADDR)	
	addi	r4, r4, LO (INTERNAL_MEM_MAP_ADDR) 
	addis   r8,0,0x0F01			/* IMMR was at 0x0f000000 */
	stw     r4,0x01a8 (r8)			/* IMMR now at 0x47000000 */
        isync 
        
        	
	/*
	 * When the PowerPC 8260 is powered on, the processor fetches the
	 * instructions located at the address 0x100. We need to jump
	 * from the address 0x100 to the Flash space.
	 */

        lis     r4, HIADJ(start)                /* load r4 with the address */
        addi    r4, r4, LO(start)               /* of start */
 
        lis     r5, HIADJ(romInit)              /* load r5 with the address */
        addi    r5, r5, LO(romInit)             /* of romInit() */
 
        lis     r6, HIADJ(ROM_TEXT_ADRS)        /* load r6 with the address */
        addi    r6, r6, LO(ROM_TEXT_ADRS)       /* of ROM_TEXT_ADRS */
 
        sub     r4, r4, r5                      /*  */
        add     r4, r4, r6
 
        mtspr   LR, r4                          /* save destination address*/
                                                /* into LR register */
        blr                                     /* jump to flash mem address */
start:

	/* set the MSR register to a known state */

	xor	r0, r0, r0		/* clear register R0 */
	isync				/* synchronize */
	mtmsr 	r0			/* clear the MSR register */
	isync				/* synchronize */

	/* program the SCCR: normal operation */
	/*
	lis	r5, HIADJ (M8260_SCCR_DFBRG_16)
	addi	r5, r5, LO (M8260_SCCR_DFBRG_16)
	lis	r6, HIADJ (M8260_SCCR (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_SCCR (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)
	*/
	
	lis	r5, 0x0
	addi	r5, r5,0x0 
	lis	r6, HIADJ (M8260_SCCR (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_SCCR (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)
	
	
	
	
	/* SYPCR - turn off the system protection stuff */

	/*addi	r5, r5, LO (M8260_SYPCR_SWTC | M8260_SYPCR_BMT \
			   | M8260_SYPCR_PBME | M8260_SYPCR_LBME) */
	addi	r5, r5, LO (0xFFFFFFC0) 		   
	lis	r6, HIADJ (M8260_SYPCR (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_SYPCR (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)

	/* program the BCR */

	addis   r5,0,0x100c
	lis	r6, HIADJ (M8260_BCR (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_BCR (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)
 
	/* program the PPC_ACR */

	addi    r5,0,0x0002
	lis	r6, HIADJ (M8260_PPC_ACR (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_PPC_ACR (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)
 
	/* program the PPC_ALRH */

	addis   r5,0,0x0126
	ori     r5,r5,0x7893
	lis	r6, HIADJ (M8260_PPC_ALRH (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_PPC_ALRH (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)
     
	/* program the SIUMCR -- ADS Pilot has DPPC set to 11 */

        addis   r5,0,0x0821       /* 0x0821 */
        ori     r5,r5,0x0000
	lis	r6, HIADJ (M8260_SIUMCR (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_SIUMCR (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)
 
	/* program the TESCR1 */

	addis   r5,0,0x0000
	ori     r5,r5,0x4000
	lis	r6, HIADJ (M8260_TESCR1 (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_TESCR1 (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)
 
	/* program the LTESCR1 */

	addis   r5,0,0x0000
	ori     r5,r5,0x4000
	lis	r6, HIADJ (M8260_LTESCR1 (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_LTESCR1 (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)
 
	/*
	 * Map the bank 0 to the flash area - On the ADS board at reset time
	 * the bank 0 is already used to map the flash.
	 */

	/* load the base register */

 	#ifdef BOOT_FILE_ROM    
        lis     r5, HIADJ (0XFF000801)      /* 8bit port size */
        addi    r5, r5, LO (0XFF000801)
	#else
        lis     r5, HIADJ (0XFF001001)      /* 16bit port size */
        addi    r5, r5, LO (0XFF001001)
 	#endif 

	lis	r6, HIADJ (M8260_BR0 (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_BR0 (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)


/* load the option register */
      
 #ifdef BOOT_FILE_ROM       
        lis     r5, HIADJ (0XFFF80856)      /* 512KBYTES */
        addi    r5, r5, LO (0XFFF80856)
 #else
        lis     r5, HIADJ (0XFF800954)      /* 4MBYTES xiyong */
        addi    r5, r5, LO (0XFF800954)
 #endif 

                          
	lis	r6, HIADJ (M8260_OR0 (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_OR0 (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)
	
SdramInit:

	/* program the MPTPR */

	addi    r5,0,0x4000
        lis     r6, HIADJ (M8260_MPTPR (INTERNAL_MEM_MAP_ADDR))
        addi    r6, r6, LO (M8260_MPTPR (INTERNAL_MEM_MAP_ADDR))
	sth     r5, 0x0 (r6)      /* store upper half-word */

	/* program the PSRT */

	addi    r5,0,0x0010      /* load 0x10 or 16 */
        lis     r6, HIADJ (M8260_PSRT (INTERNAL_MEM_MAP_ADDR))
        addi    r6, r6, LO (M8260_PSRT (INTERNAL_MEM_MAP_ADDR))
	stb     r5, 0x0 (r6)      /* store byte - bits[24-31] */
 
	/* load OR1 */

        lis     r5, HIADJ (0XF8002500) /* xiyong: For PBI=0,F8002500 ,For PBI=1,F8002B00 */
        addi    r5, r5, LO (0XF8002500)    
        lis     r6, HIADJ (M8260_OR1 (INTERNAL_MEM_MAP_ADDR))
        addi    r6, r6, LO (M8260_OR1 (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)

	/* load BR1 */

        lis     r5, HIADJ (0X00000041)
        addi    r5, r5, LO (0X00000041)			  
        lis     r6, HIADJ (M8260_BR1 (INTERNAL_MEM_MAP_ADDR))
        addi    r6, r6, LO (M8260_BR1 (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)

	/* xiyong:mod I change PBI=0, that is use bank interleaving
	 * program the PSDMR as explained below: 
	 * PBI is set to zero, since page-based interleaving is not
	 * supported on early silicon revisions
	 * Refresh services are off for now
	 * OP selects the "Precharge all banks" command
	 * SDAM = b001
	 * BSMA selects A15-A17 as bank select lines 
	 * A9 is selected as control pin for SDA10 on SDRAM
	 * 7-clock refresh recovery time
	 * precharge-to-activate interval is 3-clock time
	 * activate-to-read/write interval is 2-clock time
	 * Burst lenght is 4
	 * last data out to precharge is 1 clock
	 * write recovery time is 1 clock
	 * no external address multiplexing
	 * normal timing for the control lines
	 * CAS latency is 2
	 */