target.nr

MPC8260的vxworks BSP源码

'\" t
.so wrs.an
.\" ads8260/target.nr - Motorola MPC8260ADS target specific documentation
.\"
.\" Copyright 1984-1999 Wind River Systems, Inc.
.\"
.\" modification history
.\" --------------------
.\" 01f,21apr00,stv  changes regarding programming start flash address (PILOT) 
.\" 01e,05mar00,mtl  changes for PILOT rev of ads8260 board
.\" 01d,04oct99,ms_  fixed header to give correct file name for online man page
.\" 01c,14sep99,ms_  updated for fcs release
.\" 01b,19jul99,ms_  updated for beta release
.\" 01a,21feb99,ms_  adapted from template version 01e
.\"
.\"
.TH "ads8260" T "Motorola MPC8260ADS" "Rev: 05 Mar 2000" "VXWORKS REFERENCE MANUAL"

.SH "NAME"
.aX "Motorola MPC8260ADS"

.SH "INTRODUCTION"
This manual entry provides board-specific information necessary to run
VxWorks for the ads8260 BSP. 

The BSP will work with both rev ENG and rev PILOT of the ADS8260 board.
The default rev is PILOT, which is turned on by the macro BOARD_REV_PILOT
in config.h. Differences between the PILOT and ENG rev are noted
wherever important.

.SH "BOOT ROMS"
No VxWorks Boot ROM is provided with this BSP release. Nevertheless VxWorks
boot code is working if downloaded into the SIMM Flash ROM.

VxWorks boot code can be programmed in to Flash using one of the following
methods:

.SS "1. Directly using vbug"
Using the vbug, a bootrom image can be read from a host and programmed
directly into Flash Rom. A version of vbug which supports the PILOT rev
of the board was not available at the time of this writing.

.SS "2. From RAM using vbug"
Using the vbug, a bootrom image can be read from a host into RAM, and
then moved (programmed) into Flash Rom. A version of vbug which supports
the PILOT rev of the board was not available at the time of this writing.

.SS "3. Using Macraigor Raven"
Using the Macraigor Raven (www.macraigor.com), and their OCD Commander
host-based software a bootrom image can be read from the host and 
programmed into Flash Rom, as detailed below:

Install the Raven connector through a parallel port onto your host, and
power it on. Connect the COP interface cable from the Raven into the
ADS board's JTAG/COP connector.

Once all the connections have been made, power up the ADS board and start the
OCD Commander executable on the host. 

1. Execute the reset command to initialize the board:

.CS
	> RESET
.CE

2. Click FLASH PGM.  Wait for the flash programmer to come up.

3. Click Program.  Wait for the programming menu.

4. Click Browse and select the bootrom_uncmp.hex file.

5. Select "Erase Target Flash Sectors Before Programming".

6. Change the "Start Programming at Flash Address:" value to 0xfff00000. 

7. Click Program.  The software will erase the flash, then program it,
and finally will say Program/Verify Complete.

.SS "4. Using vxWorks"
Booting VxWorks as detailed below, and then using VxWorks to read the
bootrom image from a host and to program it into Flash Rom

This is explained below:

1. Boot VxWorks as detailed below

2. On the host, prepare a hex image of the bootrom. On a Unix host:
.CS
	make bootrom_uncmp
	elfToBin < bootrom_uncmp > buncmp.bin
	cp buncmp.bin /tmp
	ls -l buncmp.bin
.CE
Note the number of bytes given by the last step

3. Using a VxWorks shell, read and program the image. Replace the number
of bytes (359044 below) with the size of your image. Make sure the allocated
buffer is large enough:
.CS
	sysFlashErase 0
	fd1 = open ("/tmp/buncmp.bin",2,0)
	p1 = malloc (0x100000)
	read (fd1, p1, 359044)
	sysFlashWrite (p1, 359044, 0,0)
.CE

Note that the offset on the PILOT rev board will have to be 
(0xfff00000 - FLASH_ADRS). See ROM considerations below.

4. At this point the VxWorks bootrom is programmed into Flash rom. Resetting
the board should yield the familiar VxWorks boot screen.

.SH "BOOTING VXWORKS"

.SS "1. Using vbug"
Using vbug, a vxWorks image can be read from a host and loaded
into RAM.  A version of vbug which supports the PILOT rev
of the board was not available at the time of this writing.
However, the following instructions, written for and tested
on the ENG rev of the board, are included for reference:

Install the ADI card into your host, connect the ADI card
in your host to the connector labeled "ADI" on the ADI2COP board,
and connect the JTAG_PORT on the ADI2COP board to the COP-JTAG
connector on the ADS board.

5VDC must be applied to P19 on the ADS board. Note that P1 on the
ADS board is not used. Note also that the ADI2COP board requires no
power in this configuration; it receives its power from 
the connection to the host.

For more details refer to the Motorola documentation for the ADI system,
and to the MPC8260 ADS User's Manual.

Once all the connections have been made, power up the ADS board and start the
vbug executable on the host. Execute the reset command to initialize the
board:

.CS
	PQII> reset
.CE

You may get an error e.g. 

.CS
	Communication failure - failed to reset TAP controller
.CE

If this occurs simply try again; you may need to press the red power on
reset button on the ADS. If the problem persists remove power from the
ADS board, remove power from the ADI2COP by unplugging it from the host,
and exit the vbug application. Then reconnect everything and start the
vbug application again.

A successful reset results in:

.CS
	Stoppped on address fff00108
.CE

(Note: the address may be different on the PILOT board)

Next download VxWorks:

.CS
	PQII> load -fdl /<ADS860_BSP_PATH>/vxWorks
	Loading ELF file . . .
	Entry point set to 00010000
	Loading section 1 (.text) : 0009722c bytes at 00010000 
	Loading section 2 (.rodata) : 0000f4cc bytes at 000a7230 
	Loading section 4 (.data) : 0001dcc4 bytes at 000b6700 
	Loading section 5 (.ctors) : 00000008 bytes at 000d43c4 
	Loading section 6 (.dtors) : 00000008 bytes at 000d43cc 
	Loading section 7 (.got) : 00000010 bytes at 000d43d4 
	Loading section 9 (.sbss) : 000002f4 bytes at 000d43e4 (not loaded)
	Loading section 10 (.bss) : 000078c0 bytes at 000d46d8 (not loaded)
	Heap start address set to 000dbf98

.CE

And finally start VxWorks execution:

.CS
	PQII> go 00010000
.CE

.SS "Jumpers on ENG board revision"
.LP
The baud rate generator assumes a 40 MHz system clock and a
CPM multiplication factor of 2. The CPM multiplication factor is
programmed on DS1, as follows:
.TS
center;
l l
l l.
Label	Position
_
MODCK 1	Off
MODCK 2	Off
MODCK 3	Off
RESERVED	On
.TE

.SS "Jumpers on PILOT board revision"
.LP
The baud rate generator assumes a 40 MHz system clock and a
CPM multiplication factor of 2. Although the PILOT board
supports reading the Hard Reset Configuration Word from Flash
or from the BCSR, the currently shipping Pilot Board has a
processor XPC8260 rev. 0.2, which does not support reading
the Flash at Power-on or Hard reset and so must be set to
use BCSR. This setting and the CPM multiplication factor is
programmed on DS1, as follows:
.TS
center;
l l
l l.
Label   	Position
_
FLASH/BCSR	Off
MODCKH 0	On
MODCKH 1	Off
MODCKH 2	On
MODCKH 3	Off
MODCK  1	Off
MODCK  2	Off
MODCK  3	Off
.TE


On revision PILOT of the ADS8260 board, there is a new JTAG machine inserted
in front of the MPC8260's COP/JTAG port to provide fast download 
capability for the ADS. Via J5 it is possible to bypass the new JTAG machine
to be compatible with the ENG rev of the board. In the tested configuration,
a jumper is placed between positions 1-2 of J5 to enable the new JTAG
machine. 

.SH "FEATURES"

.SS "Supported Features (Both ENG and PILOT board revisions)"

SCC1 and SCC2 as a UART

FCC2 as an Ethernet device supporting 10BaseT and 100BaseT protocol

Interrupt Controller

System Clock

Baud Rate Generators as required for SCC1 and SCC2

16 MByte SDRAM DIMM on 60x bus (32 and 64 MByte configurations have not 
been tested)

DMA as required only for SCC1, SCC2, and FCC2

Auxiliary clock and timestamp clock

8 MByte Flash module (16 and 32 MByte configurations have not been tested)

Flash read and write capability

Instruction and Data caches


.SS "Unsupported Features (Both PILOT and ENG board revisions)"

virtual DMA

Parallel Ports

Baud Rate Generators not used by supported devices

SPI

I2C

4MByte SDRAM on local bus. 

Reset capability or options

SCC1 and SCC2 in any mode other than UART

SCC3 and SCC4

ATM, Transparent, or HDLC protocols on FCC2 

FCC1 and FCC3

MCC1 and MCC2

SMC1 or SMC2

Any of the eight TDM interfaces

Support for the PCI bridge (hardware not available yet)

Support for the L2 cache (hardware not available yet)

Support for the two 96 DIN connectors 
(Voyager Tools Board connector and Expansion connector) 
which bring out all pins on the MPC8260 chip

.SS "Feature Interactions"
None known

.SH "HARDWARE DETAILS"
This section documents the details of the device drivers and board
hardware elements.

.SS "Devices"
The chip drivers included are:

    m8260Sio.c - serial driver
    m8260IntrCtl.c - interrupt controller driver
    m8260Timer.c - timer driver
    motFccEnd.c - FCC Ethernet END driver
    miiLib.c - Media Independent Interface library

The BSP configures both SCC1 and SCC2 as UART devices. 
SCC1 is used as a console device.
FCC2 is used as an ethernet port. 

.SS "Memory Maps"
.LP
The following table describes the ads8260 default memory map:
.TS E
allbox expand;
lf3 lf3 lf3 lf3
l l l l .
.ne 6
.sp .5
Start	Size	End	Access to
_
0x0000_0000	16MB	0x00FF_FFFF	SDRAM DIMM on 60X bus
0x0100_0000	48MB	0x03FF_FFFF	T{
Unused (partially used when optional 32MB DIMM
is installed, and fully used when optional 64MB DIMM
is installed in place of standard 16MB DIMM)
T}
0x0400_0000	4MB	0x043F_FFFF	T{
Soldered SDRAM on local (1) bus (unsupported)
T}
0x0440_0000	1MB	0x044F_FFFF	Unused
0x0450_0000	32KB	0x0450_7FFF	T{
Board Control and Status Registers
(BCSR0 through BCSR7 on PILOT revision, BCSR0 through BCSR3 on ENG revision)
T}
0x0450_8000		0x045F_FFFF	Unused
0x0460_0000	32KB	0x0460_7FFF	ATM (unsupported)
0x0460_8000		0x046F_FFFF	Unused
0x0470_0000	64KB	0x0471_FFFF	T{
MPC 8260 Internal Memory 
(see MPC8260 PowerQUICC II User's Manual, 
Chapter 3, Memory Map, and
Chapter 13, CPM Overview, for further details, 
and see Parameter Ram below)
T}
0x0472_0000		0xFCFF_FFFF	Unused
0xFD00_0000	32MB	0xFFFF_FFFF	Flash SIMM (size optional)
.TE

.LP
The following table describes the ads8260 default usage
of the MPC8260's internal Parameter Ram, sometimes also 
called Data/Parameter Ram or DPRAM:
.TS E
allbox expand;
lf3 lf3 lf3 lf3
l l l l .
.ne 6
.sp .5
Start	Size	End	Description
_
0x0470_0000	8 bytes	0x0470_0007	SCC1 Receive Buffer Descriptor
0x0470_0000	2 bytes	0x0470_0001	SCC1 Receive Buffer Status
0x0470_0002	2 bytes	0x0470_0003	SCC1 Receive Buffer Length
0x0470_0004	4 bytes	0x0470_0007	pointer to SCC1 Receive Buffer 
0x0470_0008	8 bytes	0x0470_000F	SCC1 Transmit Buffer Descriptor
0x0470_0008	2 bytes	0x0470_0009	SCC1 Transmit Buffer Status
0x0470_000A	2 bytes	0x0470_000B	SCC1 Transmit Buffer Length
0x0470_000C	4 bytes	0x0470_000F	pointer to SCC1 Transmit Buffer 

0x0470_0040	1 bytes	0x0470_0040	SCC1 Receive Buffer 
0x0470_0060	1 bytes	0x0470_0060	SCC1 Transmit Buffer 

0x0470_0100	8 bytes	0x0470_0107	SCC2 Receive Buffer Descriptor
0x0470_0100	2 bytes	0x0470_0101	SCC2 Receive Buffer Status
0x0470_0102	2 bytes	0x0470_0103	SCC2 Receive Buffer Length
0x0470_0104	4 bytes	0x0470_0107	pointer to SCC2 Receive Buffer 
0x0470_0108	8 bytes	0x0470_010F	SCC2 Transmit Buffer Descriptor
0x0470_0108	2 bytes	0x0470_0109	SCC2 Transmit Buffer Status
0x0470_010A	2 bytes	0x0470_010B	SCC2 Transmit Buffer Length
0x0470_010C	4 bytes	0x0470_010F	pointer to SCC2 Transmit Buffer 

0x0470_0140	1 bytes	0x0470_0140	SCC2 Receive Buffer 
0x0470_0160	1 bytes	0x0470_0160	SCC2 Transmit Buffer 
.TE

.LP
The following table describes the default VxWorks macros which
are used to address memory
.TS E
expand;
lf3 lf3 lf3
l l l .
.ne 6
.sp .5
Macro Name	Macro Definition	Description
_
LOCAL_MEM_LOCAL_ADRS	0x0000_0000	Base of RAM
RAM_LOW_ADRS	T{
LOCAL_MEM_LOCAL_ADRS + 0x0001_0000
T}	T{
VxWorks image loaded here. Stack grows down from this address.
T}
RAM_HIGH_ADRS	T{
LOCAL_MEM_LOCAL_ADRS + 0x0020_0000
T}	T{
VxWorks bootrom loaded here.
T}
LOCAL_MEM_SIZE	0100_0000	Default 16 MBytes of RAM
DEFAULT_BCSRS_ADRS	0450_0000	T{
Default location of Board Control and Status Registers on ENG rev
T}
BCSR_BASE_ADRS	0450_0000	T{
Default location of Board Control and Status Registers on PILOT rev
T}
BCSRS_ADRS_SIZE	0001_0000	64 KBytes on ENG rev
BCSRS_SIZE	0001_0000	64 KBytes on PILOT rev
DEFAULT_IMM_ADRS	0470_0000	T{
Default location of MPC 8260 Internal Memory Map
T}
IMM_SIZE	0x20000	T{
128K Internal Memory Map Size
T}
ROM_BASE_ADRS	0xFFF0_0000	Base address of ROM on PILOT rev
ROM_BASE_ADRS	0xFF80_0000	Base address of ROM on ENG rev
ROM_TEXT_ADRS	T{
ROM_BASE_ADRS + 0x100
T}	T{
Text must start after vector table
T}
ROM_WARM_ADRS	T{
ROM_TEXT_ADRS + 8