ethernet.h

MPC8260的vxworks BSP源码

/*-----------------------------------------------------------------------               
*
* File:  ethernet.h
*
* Description:  
*
*       Constants and Definitions for MPC8260 Fast Ethernet Example.
*
*
*  
*
*-----------------------------------------------------------------------*/



/*----------------------------------------------------------------------*/
/*                   MPC8260 CONSTANTS AND DEFINITIONS                  */
/*----------------------------------------------------------------------*/

#define BASE_EVT 0x0        /* Base Address of Exception Vector Table */

#define EXT_INT_VECTOR ((BASE_EVT) + 0x500)  /* Base address of external 
                                                interrupt code */

#define NEXT_VECTOR (EXT_INT_VECTOR + 0x100)



/*----------------------------------------------------------------------*/
/*                APPLICATION CONSTANTS AND DEFINITIONS                 */
/*----------------------------------------------------------------------*/

#define BASE_ADDR   0x47000000 /* On the VADS board, the hard reset config
                                 word places the IMM at 0xF0000000, and is
                                 then relocated to 0x47000000 */



/*----------------------------------------*/
/* Constants and Definitions for Ethernet */
/*----------------------------------------*/

#define ENET_C_PRES    0xFFFFFFFF    /* CRC Preset */
#define ENET_C_MASK    0xDEBB20E3    /* Constant MASK for CRC */
#define ENET_MFLR      1518          /* Ethernet Max Frame Length */
#define ENET_MINFLR    64            /* Ethernet Min Frame Length */
#define ENET_MDMA      1520          /* Max DMA length */
#define ENET_RET_LIM   15            /* Retry Limit Threshold */
#define ENET_PAD       0x8888        /* Pad Characters */
#define ENET_DSR       0xD555        /* DSR value for Ethernet */
#define ENET_PADDR_H   0x5548        /* Physical Address 1 (MSB) */
#define ENET_PADDR     0x3322        /* Physical Address */
#define ENET_PADDR_L   0x1900        /* Physical Address 1 (LSB) */
#define ENET_MRBLR     288           /* Max. Receive Buffer Length
                                        (arbitrarily a little longer
                                        than expected BD size for this
                                        example) */
#define TXBUFINDEX     8

 
/*----------------------------------------------*/
/* Board Control and Status Register (for ADS) */
/*----------------------------------------------*/

/*
typedef struct bcsr 

{
	UWORD  bcsr0; 
	UWORD  bcsr1;
	UWORD  bcsr2;
	UWORD  bcsr3;

} t_BCSR;
*/

/* BCSR bit definitions */ 

#define GREEN 2
#define GP_LED0_PIL 0x02000000
#define GP_LED0_ENG 0x2

#define RED 1
#define GP_LED1_PIL 0x01000000
#define GP_LED1_ENG 0x1



/*--------------------------------*/
/* Size of buffers in buffer pool */
/*--------------------------------*/

#define BUFFER_SIZE 256

/*---------------------------------------------------*/
/* Number of Receive and Transmit Buffer Descriptors */
/*---------------------------------------------------*/

#define NUM_RXBDS 8
#define NUM_TXBDS 8



/*-------------------*/
/* Buffer components */
/*-------------------*/

#define BDRING_BASE 0x00100000

typedef UBYTE LB[ENET_MRBLR + 32];  /* MRBLR + 
                                       32 bytes extra for extra DMA, here ENET_MRBLR=288 */

#define MAX_TXBD_INDEX  16
#define FIRST_TX_BUF 8

typedef struct BufferDescriptor 

{
   UHWORD bd_cstatus;     /* control and status */
   UHWORD bd_length;      /* transfer length */
   UBYTE  *bd_addr;       /* buffer address */

} BD;


typedef struct BufferDescRings 

{
    BD RxBD[NUM_RXBDS];    /* Rx BD ring */
    BD TxBD[NUM_TXBDS];    /* Tx BD ring */

} BDRINGS;


#define BD_RX_ERROR 0xBF    /* Mask for set of Receive Buffer Errors,
                               including: DE, LG, NO, AB, CR, OV, CD */
                               
                               

/*-----------------------------------------------------------------*/
/* Number of Instructions in Vector Table for particular Interrupt */
/*-----------------------------------------------------------------*/

#define VECTOR_BLOCK_LEN 0x100



/*------------------*/
/* Additional Masks */
/*------------------*/

/* GFMR MASKS */

#define GFMR_ENT  0x00000020
#define GFMR_ENR  0x00000010


/* CPM_CPCR MASKS */

#define CPCR_FLG                0x00010000
#define CPCR_FCC2_CH            0x16200000
#define CPCR_FCC3_CH            0x1a400000
#define CPCR_GRSTOP_TX          0x00000005
#define CPCR_INIT_TX_RX_PARAMS  0x00000000
#define CPCR_MCN_FEC            0x00000300
#define READY_TO_RX_CMD         0  /* Ready to receive a command */


/* INTERRUPT CONTROL */
#define SIMR_L_FCC2     0x40000000
#define SIVEC_FCC2  33


/* GENERAL PURPOSE */
#define  ALL_ONES    0xFFFFFFFF
#define  ALL_ZEROS   0x00000000

/* FCC ethernet RxBD */
#define RX_BD_E      0x8000
#define RX_BD_RES    0x4000
#define RX_BD_W      0x2000
#define RX_BD_I      0x1000
#define RX_BD_L      0x0800
#define RX_BD_F      0x0400
#define RX_BD_RES1   0x0200
#define RX_BD_M      0x0100
#define RX_BD_BC     0x0080
#define RX_BD_MC     0x0040	
#define RX_BD_LG     0x0020
#define RX_BD_NO     0x0010
#define RX_BD_SH     0x0008
#define RX_BD_CR     0x0004
#define RX_BD_OV     0x0002
#define RX_BD_CL     0x0001


/* FCC ethernet TxBD */
#define TX_BD_R      0x8000
#define TX_BD_PAD    0x4000
#define TX_BD_W      0x2000
#define TX_BD_I      0x1000
#define TX_BD_L      0x0800
#define TX_BD_TC     0x0400
#define TX_BD_DEF    0x0200
#define TX_BD_HB     0x0100
#define TX_BD_LC     0x0080
#define TX_BD_RL     0x0040
#define TX_BD_RC     0x003c
#define TX_BD_UN     0x0002
#define TX_BD_CSL    0x0001