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📄 ad9850.lst

📁 用avr调AD9850的DDS的资料!一个很稳定的信号源!
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__text_start:
__start:
    0049 EFCF      LDI	R28,0xFF
    004A E1D0      LDI	R29,0x10
    004B BFCD      OUT	0x3D,R28
    004C BFDE      OUT	0x3E,R29
    004D 51C0      SUBI	R28,0x10
    004E 40D0      SBCI	R29,0
    004F EA0A      LDI	R16,0xAA
    0050 8308      STD	Y+0,R16
    0051 2400      CLR	R0
    0052 E0E6      LDI	R30,6
    0053 E0F1      LDI	R31,1
    0054 E011      LDI	R17,1
    0055 30E6      CPI	R30,6
    0056 07F1      CPC	R31,R17
    0057 F011      BEQ	0x005A
    0058 9201      ST	R0,Z+
    0059 CFFB      RJMP	0x0055
    005A 8300      STD	Z+0,R16
    005B E8EC      LDI	R30,0x8C
    005C E0F0      LDI	R31,0
    005D E0A0      LDI	R26,0
    005E E0B1      LDI	R27,1
    005F E010      LDI	R17,0
    0060 39E2      CPI	R30,0x92
    0061 07F1      CPC	R31,R17
    0062 F021      BEQ	0x0067
    0063 95C8      LPM
    0064 9631      ADIW	R30,1
    0065 920D      ST	R0,X+
    0066 CFF9      RJMP	0x0060
    0067 940E00D6  CALL	_main
_exit:
    0069 CFFF      RJMP	_exit
FILE: E:\mcu\avr\test\AD9850\chuan9850.c
(0001) /*RESET=pa0 WCLK=pa2 FQUD=pa1 D7=PA3 */
(0002) #include<iom128v.h>
(0003) #include<macros.h>
(0004) //char str[]={0x00,0x00,0x3d,0x70,0xa3,0xd7};//30m
(0005) //char str[]={0x00,0x00,0x05,0x62,0x4d,0xd2};//40m
(0006) char str[]={0x00,0x00,0x4d,0x70,0xa3,0xd7};//30m
(0007) void set_wclk(unsigned char i)
(0008) {
(0009)  if(i) PORTA|=0X04;
_set_wclk:
  i                    --> R16
    006A 2300      TST	R16
    006B F011      BEQ	0x006E
    006C 9ADA      SBI	0x1B,2
    006D C003      RJMP	0x0071
(0010)  else  PORTA&=0XFb;
    006E B38B      IN	R24,0x1B
    006F 7F8B      ANDI	R24,0xFB
    0070 BB8B      OUT	0x1B,R24
    0071 9508      RET
(0011) }
(0012) void set_fqud(unsigned char i)
(0013) {
(0014)  if(i) PORTA|=0X02;
_set_fqud:
  i                    --> R16
    0072 2300      TST	R16
    0073 F011      BEQ	0x0076
    0074 9AD9      SBI	0x1B,1
    0075 C003      RJMP	0x0079
(0015)  else  PORTA&=0XFd;
    0076 B38B      IN	R24,0x1B
    0077 7F8D      ANDI	R24,0xFD
    0078 BB8B      OUT	0x1B,R24
    0079 9508      RET
(0016) }
(0017) void set_reset(unsigned char i)
(0018) {
(0019)  if(i) PORTA|=0X01;
_set_reset:
  i                    --> R16
    007A 2300      TST	R16
    007B F011      BEQ	0x007E
    007C 9AD8      SBI	0x1B,0
    007D C003      RJMP	0x0081
(0020)  else  PORTA&=0XFE;
    007E B38B      IN	R24,0x1B
    007F 7F8E      ANDI	R24,0xFE
    0080 BB8B      OUT	0x1B,R24
    0081 9508      RET
(0021) }
(0022) void set_d7(unsigned char i)
(0023) {
(0024)  if(i) PORTA|=0X08;
_set_d7:
  i                    --> R16
    0082 2300      TST	R16
    0083 F011      BEQ	0x0086
    0084 9ADB      SBI	0x1B,3
    0085 C003      RJMP	0x0089
(0025)  else  PORTA&=0XF7;
    0086 B38B      IN	R24,0x1B
    0087 7F87      ANDI	R24,0xF7
    0088 BB8B      OUT	0x1B,R24
    0089 9508      RET
_chuli:
  i                    --> R20
  com                  --> R22
    008A 940E00E6  CALL	push_gset2
    008C 2F60      MOV	R22,R16
(0026) }
(0027) void chuli(unsigned char com)
(0028) {
(0029)  unsigned char i;
(0030)  set_wclk(0);
    008D 2700      CLR	R16
    008E DFDB      RCALL	_set_wclk
(0031)  for(i=0;i<8;i++)
    008F 2744      CLR	R20
    0090 C00D      RJMP	0x009E
(0032)   {
(0033)    if(com|0xfe==0xff)//要移的位为低位
    0091 2366      TST	R22
    0092 F019      BEQ	0x0096
(0034)     {set_d7(1);}
    0093 E001      LDI	R16,1
    0094 DFED      RCALL	_set_d7
    0095 C002      RJMP	0x0098
(0035)    else
(0036)     {set_d7(0);}
    0096 2700      CLR	R16
    0097 DFEA      RCALL	_set_d7
(0037)    com>>=1;
    0098 9566      LSR	R22
(0038)    set_wclk(1);
    0099 E001      LDI	R16,1
    009A DFCF      RCALL	_set_wclk
(0039)    set_wclk(0);	
    009B 2700      CLR	R16
    009C DFCD      RCALL	_set_wclk
    009D 9543      INC	R20
    009E 3048      CPI	R20,0x8
    009F F388      BCS	0x0091
    00A0 940E00DD  CALL	pop_gset2
    00A2 9508      RET
_ad9850:
  i                    --> R20
    00A3 940E00E8  CALL	push_gset1
(0040)   }
(0041) }  
(0042) void ad9850()
(0043) {
(0044)  unsigned char i;
(0045)  set_fqud(0);
    00A5 2700      CLR	R16
    00A6 DFCB      RCALL	_set_fqud
(0046)  for(i=5;i>0;i--)
    00A7 E045      LDI	R20,5
    00A8 C009      RJMP	0x00B2
(0047)   {chuli(str[i]);}
    00A9 E080      LDI	R24,0
    00AA E091      LDI	R25,1
    00AB 2FE4      MOV	R30,R20
    00AC 27FF      CLR	R31
    00AD 0FE8      ADD	R30,R24
    00AE 1FF9      ADC	R31,R25
    00AF 8100      LDD	R16,Z+0
    00B0 DFD9      RCALL	_chuli
    00B1 954A      DEC	R20
    00B2 2422      CLR	R2
    00B3 1624      CP	R2,R20
    00B4 F3A0      BCS	0x00A9
(0048)  set_fqud(1);
    00B5 E001      LDI	R16,1
    00B6 DFBB      RCALL	_set_fqud
(0049)  set_fqud(0); 
    00B7 2700      CLR	R16
    00B8 DFB9      RCALL	_set_fqud
    00B9 940E00EB  CALL	pop_gset1
    00BB 9508      RET
(0050) }
(0051) void setup()
(0052) {
(0053)   set_wclk(0);
_setup:
    00BC 2700      CLR	R16
    00BD DFAC      RCALL	_set_wclk
(0054)   set_fqud(0);
    00BE 2700      CLR	R16
    00BF DFB2      RCALL	_set_fqud
(0055)   set_wclk(1);
    00C0 E001      LDI	R16,1
    00C1 DFA8      RCALL	_set_wclk
(0056)   set_wclk(0);
    00C2 2700      CLR	R16
    00C3 DFA6      RCALL	_set_wclk
(0057)   set_fqud(1);
    00C4 E001      LDI	R16,1
    00C5 DFAC      RCALL	_set_fqud
(0058)   set_fqud(0);
    00C6 2700      CLR	R16
    00C7 DFAA      RCALL	_set_fqud
    00C8 9508      RET
(0059) }
(0060) void m128_init()
(0061) {
(0062)  DDRA=0XFF;
_m128_init:
    00C9 EF8F      LDI	R24,0xFF
    00CA BB8A      OUT	0x1A,R24
(0063)  PORTA=0XFF;
    00CB BB8B      OUT	0x1B,R24
(0064)  DDRB=0X00;
    00CC 2422      CLR	R2
    00CD BA27      OUT	0x17,R2
(0065)  PORTB=0XFF;
    00CE BB88      OUT	0x18,R24
(0066)  DDRC=0X00;
    00CF BA24      OUT	0x14,R2
(0067)  PORTC=0XFF;
    00D0 BB85      OUT	0x15,R24
(0068)  DDRD=0X00;
    00D1 BA21      OUT	0x11,R2
(0069)  PORTD=0XFF;
    00D2 BB82      OUT	0x12,R24
(0070)  DDRE=0X00;
    00D3 B822      OUT	0x02,R2
(0071)  PORTE=0XFF;
    00D4 B983      OUT	0x03,R24
    00D5 9508      RET
(0072) }
(0073) void main()
(0074) {
(0075)  m128_init();
_main:
    00D6 DFF2      RCALL	_m128_init
(0076)  set_reset(0);
    00D7 2700      CLR	R16
    00D8 DFA1      RCALL	_set_reset
(0077)  setup();
    00D9 DFE2      RCALL	_setup
(0078)  ad9850();
    00DA DFC8      RCALL	_ad9850
(0079)  while(1);
FILE: <library>
    00DB CFFF      RJMP	0x00DB
    00DC 9508      RET
pop_gset2:
    00DD E0E2      LDI	R30,2
    00DE 940C00EC  JMP	pop
push_gset5:
    00E0 92FA      ST	R15,-Y
    00E1 92EA      ST	R14,-Y
push_gset4:
    00E2 92DA      ST	R13,-Y
    00E3 92CA      ST	R12,-Y
push_gset3:
    00E4 92BA      ST	R11,-Y
    00E5 92AA      ST	R10,-Y
push_gset2:
    00E6 937A      ST	R23,-Y
    00E7 936A      ST	R22,-Y
push_gset1:
    00E8 935A      ST	R21,-Y
    00E9 934A      ST	R20,-Y
    00EA 9508      RET
pop_gset1:
    00EB E0E1      LDI	R30,1
pop:
    00EC 9149      LD	R20,Y+
    00ED 9159      LD	R21,Y+
    00EE FDE0      SBRC	R30,0
    00EF 9508      RET
    00F0 9169      LD	R22,Y+
    00F1 9179      LD	R23,Y+
    00F2 FDE1      SBRC	R30,1
    00F3 9508      RET
    00F4 90A9      LD	R10,Y+
    00F5 90B9      LD	R11,Y+
    00F6 FDE2      SBRC	R30,2
    00F7 9508      RET
    00F8 90C9      LD	R12,Y+
    00F9 90D9      LD	R13,Y+
    00FA FDE3      SBRC	R30,3
    00FB 9508      RET
    00FC 90E9      LD	R14,Y+
    00FD 90F9      LD	R15,Y+
    00FE 9508      RET

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