📄 i950.h
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unsigned char RegNum;
unsigned char DeviceNum;
unsigned short Reserved;
} sHostAdr;
unsigned long lHostAdr;
} HOST_ADR;
typedef struct _HCSinfo {
ULONG base;
UCHAR vec;
UCHAR bios; /* High byte of BIOS address */
USHORT BaseAndBios; /* high byte: pHcsInfo->bios,low byte:pHcsInfo->base */
} HCSINFO ;
/*
typedef struct _TargetInfo {
ULONG ID;
ULONG scbCnt;
}TARGETINFO;
*/
/*------------------------------------------------------*/
/* Tulip */
/*------------------------------------------------------*/
/* from tid and lun to taregt_ix */
#define TUL_TIDLUN_TO_IX( tid, lun ) ( uchar )( (tid) + ((lun)<<3) )
/* from tid to target_id */
#define TUL_TID_TO_TARGET_ID( tid ) ( uchar )( 0x01 << (tid) )
#define MAX_OFFSET 15
/**********************************************************/
/* Tulip Configuration Register Set */
/**********************************************************/
#define TUL_PVID 0x00 /* Vendor ID */
#define TUL_VENDOR_ID 0x1101 /* Tulip vendor ID */
#define TUL_PDID 0x02 /* Device ID */
#define TUL_DEVICE_ID 0x9500 /* Tulip device ID */
#define TUL_COMMAND 0x04 /* Command */
/* bit definition for Command register of Configuration Space Header */
#define BUSMS 0x04 /* BUS MASTER Enable */
#define IOSPA 0x01 /* IO Space Enable */
#define TUL_STATUS 0x06 /* status register */
#define TUL_REVISION 0x08 /* Revision number */
#define TUL_BASE 0x10 /* Base address */
#define TUL_BIOS 0x30 /* Expansion ROM base address */
#define TUL_INT_NUM 0x3C /* Interrupt line */
#define TUL_INT_PIN 0x3D /* Interrupt pin */
/**********************************************************/
/* Tulip Register Set */
/**********************************************************/
#define TUL_HACFG0 0x40 /* H/A Configuration Register 0 */
#define TUL_HACFG1 0x41 /* H/A Configuration Register 1 */
#define WIDE_SCSI_CARD 0x40 /* bit 6 tighed to high if wide card */
#define TUL_HACFG2 0x42 /* H/A Configuration Register 2 */
#define TUL_HACFG3 0x43 /* H/A Configuration Register 3 */
#define TUL_SDCFG0 0x44 /* SCSI Device Configuration 0 */
#define TUL_SDCFG1 0x45 /* SCSI Device Configuration 1 */
#define TUL_SDCFG2 0x46 /* SCSI Device Configuration 2 */
#define TUL_SDCFG3 0x47 /* SCSI Device Configuration 3 */
#define TUL_GINTS 0x50 /* Global Interrupt Status Register */
#define TUL_GIMSK 0x52 /* Global Interrupt MASK Register */
#define TUL_GCTRL 0x54 /* Global Control Register */
/* ; bit definition for TUL_GCTRL */
#define EXTSG 0x80
#define EXTAD 0x60
#define SEG4K 0x08
#define EEPRG 0x04
#define MRMUL 0x02
#define TUL_GCTRLH 0x55 /* Global Control Register high byte */
#define ATDEN 0x01 /* Autotermination detection enable */
#define TUL_GSTAT 0x56 /* Global Status Register */
#define TUL_DMACFG 0x5B /* DMA configuration */
#define TUL_NVRAM 0x5D /* Nvram port address */
/**********************************************************/
/* Pass-Through SCSI Register Set */
/**********************************************************/
#define TUL_SCnt0 0x80 /* 00 R/W Transfer Counter Low */
#define TUL_SCnt1 0x81 /* 01 R/W Transfer Counter Mid */
#define TUL_SCnt2 0x82 /* 02 R/W Transfer Count High */
#define TUL_SFifoCnt 0x83 /* 03 R FIFO counter */
#define TUL_SIntEnable 0x84 /* 03 W Interrupt enble */
#define TUL_SInt 0x84 /* 04 R Interrupt Status Register */
/* bit definition for Tulip SCSI Interrupt Register */
#define TSS_RESEL_INT 0x80 /* Reselected interrupt */
#define TSS_SEL_TIMEOUT 0x40 /* Selected/reselected timeout */
#define TSS_BUS_SERV 0x20
#define TSS_SCSIRST_INT 0x10 /* SCSI bus reset detected */
#define TSS_DISC_INT 0x08 /* Disconnected interrupt */
#define TSS_SEL_INT 0x04 /* Select interrupt */
#define TSS_SCAM_SEL 0x02 /* SCAM selected */
#define TSS_FUNC_COMP 0x01
#define TUL_SCtrl0 0x85 /* 05 W Control 0 */
/*bit definition for Tulip SCSI Control 0 Register */
#define TSC_FLUSH_FIFO 0x50 /* Clear FIFO & reset OFFset counter */
#define TSC_FLUSHFIFO 0x10 /* Clear FIFO */
#define TSC_RST_SEQ 0x20 /* Reset sequence counter */
#define TSC_ABT_CMD 0x04 /* Abort command (sequence) */
#define TSC_RST_CHIP 0x02 /* Reset SCSI Chip */
#define TSC_RST_BUS 0x01 /* Reset SCSI Bus */
#define TUL_SStatus0 0x85 /* 05 R Status 0 */
/* bit definition for Tulip SCSI Status 0 Register */
#define TSS_INT_PENDING 0x80 /* Interrupt pending */
#define TSS_SEQ_ACTIVE 0x40 /* Sequencer active */
#define TSS_XFER_CNT 0x20 /* Transfer counter zero */
#define TSS_FIFO_EMPTY 0x10 /* FIFO empty */
#define TSS_PAR_ERROR 0x08 /* SCSI parity error */
#define TSS_PH_MASK 0x07 /* SCSI phase mask */
#define TUL_SCtrl1 0x86 /* 06 W Control 1 */
/* bit definition for Tulip SCSI Control 1 Register */
#define TSC_EN_SCAM 0x80 /* Enable SCAM */
#define TSC_NIDARB 0x40 /* no ID for arbitration */
#define TSC_EN_LOW_RESELECT 0x20 /* Enable low level reselect */
#define TSC_PWDN 0x10 /* Power down mode */
#define TSC_WIDE_CPU 0x08 /* Wide CPU */
#define TSC_HW_RESELECT 0x04 /* Enable HW reselect */
#define TSC_EN_BUS_OUT 0x02 /* Enable SCSI data bus out latch */
#define TSC_EN_BUS_IN 0x01 /* Enable SCSI data bus in latch */
#define TUL_SStatus1 0x86 /* 06 R Status 1 */
/* bit definition for Tulip SCSI Status 1 Register */
#define TSS_STATUS_RCV 0x80 /* Status received */
#define TSS_MSG_SEND 0x40 /* Message sent */
#define TSS_CMD_PH_CMP 0x20 /* Data phase done */
#define TSS_DATA_PH_CMP 0x10 /* Data phase done */
#define TSS_STATUS_SEND 0x08 /* Status sent */
#define TSS_XFER_CMP 0x04 /* Transfer completed */
#define TSS_SEL_CMP 0x02 /* Selection completed */
#define TSS_ARB_CMP 0x01 /* Arbitration completed */
#define TUL_SConfig 0x87 /* 07 W Configuration */
/* bit definition for Tulip SCSI Configuration Register */
#define TSC_EN_LATCH 0x80 /* Enable phase latch */
#define TSC_INITIATOR 0x40 /* Initiator mode */
#define TSC_EN_SCSI_PAR 0x20 /* Enable SCSI parity */
#define TSC_DMA_8BIT 0x10 /* Alternate dma 8-bits mode */
#define TSC_DMA_16BIT 0x08 /* Alternate dma 16-bits mode */
#define TSC_EN_WDACK 0x04 /* Enable DACK while wide SCSI xfer */
#define TSC_ALT_PERIOD 0x02 /* Alternate sync period (Fast 20) mode */
#define TSC_DIS_SCSIRST 0x01 /* Disable SCSI bus reset us */
#define TSC_INITDEFAULT TSC_INITIATOR | TSC_EN_LATCH | TSC_ALT_PERIOD | TSC_DIS_SCSIRST
#define TSC_INITDEFAULT_ALT0 TSC_INITIATOR | TSC_EN_LATCH | TSC_DIS_SCSIRST
#define TSC_WIDE_SCSI 0x80 /* Enable Wide SCSI */
#define TUL_SStatus2 0x87 /* 07 R Status 2 */
/* bit definition for Tulip SCSI Status 2 Register */
#define TSS_CMD_ABTED 0x80 /* Command aborted */
#define TSS_OFFSET_0 0x40 /* Offset counter zero */
#define TSS_FIFO_FULL 0x20 /* FIFO full */
#define TSS_TIMEOUT_0 0x10 /* Timeout counter zero */
#define TSS_BUSY_RLS 0x08 /* Busy release */
#define TSS_PH_MISMATCH 0x04 /* Phase mismatch */
#define TSS_SCSI_BUS_EN 0x02 /* SCSI data bus enable */
#define TSS_SCSIRST 0x01 /* SCSI bus reset in progress */
#define TUL_SPeriodOffset 0x88 /* 08 W wide/narrow,Sync. Transfer Period & Offset */
#define TUL_SOffsetRoomCtr 0x88 /* 08 R Offset and room counter */
#define TUL_SScsiId 0x89 /* 09 W SCSI ID */
#define TUL_SBusId 0x89 /* 09 R SCSI BUS ID */
#define TUL_STimeOut 0x8A /* 0A W Sel/Resel Time Out Register */
#define TUL_SIdent 0x8A /* 0A R Identify Message Register */
#define TUL_SAvail 0x8A /* 0A R Availiable Counter Register */
#define TUL_SData 0x8B /* 0B R/W SCSI data in/out */
#define TUL_SFifo 0x8C /* 0C R/W FIFO */
#define TUL_SSignal 0x90 /* 10 R/W SCSI signal in/out */
/* bit definition for Tulip SCSI signal Register */
#define TSC_RST_ACK 0x00 /* Release ACK signal */
#define TSC_RST_ATN 0x00 /* Release ATN signal */
#define TSC_RST_BSY 0x00 /* Release BSY signal */
#define TSC_SET_REQ 0x80 /* REQ signal */
#define TSC_SET_ACK 0x40 /* ACK signal */
#define TSC_SET_BSY 0x20 /* BSY signal */
#define TSC_SET_SEL 0x10 /* SEL signal */
#define TSC_SET_ATN 0x08 /* ATN signal */
#define TSC_SET_MSG 0x04 /* MSG signal */
#define TSC_SET_CD 0x02 /* C/D signal */
#define TSC_SET_IO 0x01 /* I/O signal */
#define TSC_REQI 0x80 /* REQ signal */
#define TSC_ACKI 0x40 /* ACK signal */
#define TSC_BSYI 0x20 /* BSY signal */
#define TSC_SELI 0x10 /* SEL signal */
#define TSC_ATNI 0x08 /* ATN signal */
#define TSC_MSGI 0x04 /* MSG signal */
#define TSC_CDI 0x02 /* C/D signal */
#define TSC_IOI 0x01 /* I/O signal */
#define TUL_SCmd 0x91 /* 11 R/W Command */
/* Command Codes of Tulip SCSI Command register */
/*#define TSC_EN_RESEL_1 0x8D */ /* Enable Reselection */
#define TSC_EN_RESEL 0x80 /* Enable Reselection */
#define TSC_CMD_COMP 0x84 /* Command Complete Sequence */
#define TSC_SEL 0x01 /* Select Without ATN Sequence */
#define TSC_SEL_ATN 0x11 /* Select With ATN Sequence */
#define TSC_SEL_ATN_DMA 0x51 /* Select With ATN Sequence with DMA */
#define TSC_SEL_ATN3 0x31 /* Select With ATN3 Sequence */
#define TSC_SEL_ATNSTOP 0x12 /* Select With ATN and Stop Sequence */
#define TSC_SELATNSTOP 0x1E /* Select With ATN and Stop Sequence */
#define TSC_SEL_ATN_DIRECT_IN 0x95 /* Select With ATN Sequence */
#define TSC_SEL_ATN_DIRECT_OUT 0x15 /* Select With ATN Sequence */
#define TSC_SEL_ATN3_DIRECT_IN 0xB5 /* Select With ATN3 Sequence */
#define TSC_SEL_ATN3_DIRECT_OUT 0x35 /* Select With ATN3 Sequence */
#define TSC_XF_DMA_OUT_DIRECT 0x06 /* DMA Xfer Infomation out */
#define TSC_XF_DMA_IN_DIRECT 0x86 /* DMA Xfer Infomation in */
#define TSC_XF_DMA_OUT 0x43 /* DMA Xfer Infomation out */
#define TSC_XF_DMA_IN 0xC3 /* DMA Xfer Infomation in */
#define TSC_XF_FIFO_OUT 0x03 /* FIFO Xfer Infomation out */
#define TSC_XF_FIFO_IN 0x83 /* FIFO Xfer Infomation in */
#define TSC_MSG_ACCEPT 0x0F /* Message Accept */
#define TUL_STest0 0x92 /* 12 R/W Test0 */
#define TUL_STest1 0x93 /* 12 R/W Test1 */
#define TUL_SConf1 0x94 /* SCSI Configuration 1 */
/**********************************************************/
/* DMA operating Register Set */
/**********************************************************/
#define TUL_XAddH 0xC0 /*DMA Transfer Physical Address */
#define TUL_XAddW 0xC8 /*DMA Current Transfer Physical Address */
#define TUL_XCntH 0xD0 /*DMA Transfer Counter */
#define TUL_XCntH2 0xD2 /*DMA Transfer Counter */
#define TUL_XCntW 0xD4 /*DMA Current Transfer Counter */
#define TUL_XCmd 0xD8 /*DMA Command Register */
/* Command Codes of DMA Command register */
#define TAX_X_FORC 0x02
#define TAX_X_ABT 0x04
#define TAX_X_CLR_FIFO 0x08
#define TAX_X_IN 0x21
#define TAX_X_OUT 0x01
#define TAX_SG_IN 0xA1
#define TAX_SG_OUT 0x81
#define TUL_Int 0xDC /*Interrupt Register */
/* Tulip DMA Interrupt Register */
#define XCMP 0x01
#define FCMP 0x02
#define XABT 0x04
#define XERR 0x08
#define SCMP 0x10
#define IPEND 0x80
#define TUL_XStatus 0xDD /*DMA status Register */
/* Tulip DMA Status Register */
#define XPEND 0x01 /* Transfer pending */
#define FEMPTY 0x02 /* FIFO empty */
#define TUL_XFifoCnt 0xDE /*DMA FIFO count */
#define TUL_Mask 0xE0 /*Interrupt Mask Register */
#define TUL_XCtrl 0xE4 /*DMA Control Register */
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