📄 ini910u.c
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TUL_WR(TulSCmd, TSC_XF_FIFO_IN);
if ((phase = wait_tulip(hcsp)) == -1)
return phase;
/* Is still parity error ? */
if (!(hcsp->JSStatus0 & TSS_PAR_ERROR) )
return phase;
}
}
return bad_seq(hcsp);
}
/****************** int_busfree rtn ********************************************/
/* scsi bus free */
char int_busfree(hcsp)
register HCS *hcsp;
{
register TULSCB *scbp;
ULONG_PTR TulSCmd;
TulSCmd = hcsp->Base + TUL_SCmd;
scbp = hcsp->ActScb;
if (scbp = hcsp->ActScb) {
hcsp->ActScb = NULL;
hcsp->ActTcs = NULL;
if (scbp->Status & TULSCB_SELECT) { /* selection timeout */
if (scbp != ll_pop_pend_scb(hcsp)) {
TulPanic("int_busfree: scbp != ll_pop_pend_scb(hcsp)\n");
}
scbp->Status = TULSCB_DONE;
scbp->HaStat = HOST_SEL_TOUT;
ll_append_done_scb(hcsp, scbp);
} else { /* unexpected bus free */
ll_unlink_busy_scb(hcsp, scbp);
scbp->Status = TULSCB_DONE;
scbp->HaStat = HOST_BUS_FREE;
ll_append_done_scb(hcsp, scbp);
}
}
TUL_WR(hcsp->Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* flush SCSI FIFO */
TUL_WR(hcsp->Base + TUL_SCtrl1, TSC_HW_RESELECT ) ;/* Enable HW reselect */
return - 1; /* 07/31/97 */
}
/***************************************************************************/
/* scsi bus reset */
char int_scsi_rst(hcsp)
register HCS *hcsp;
{
int i;
/* if DMA xfer is pending, abort DMA xfer */
if (TUL_RD(hcsp->Base, TUL_XStatus) & XPEND) {
/* Abort Bus Master xfering */
TUL_WR(hcsp->Base + TUL_XCmd, TAX_X_ABT | TAX_X_CLR_FIFO);
/* wait Abort DMA xfer done */
while ((TUL_RD(hcsp->Base, TUL_Int) & XABT) == 0) {
}
}
/* reset tulip chip */
TUL_WR( hcsp->Base + TUL_SCtrl0, TSC_RST_CHIP);
se2_wait(hcsp); /* wait 30 us */
TUL_WR( hcsp->Base + TUL_SIntEnable, 0xFF);
/* selection time out = 250 ms */
TUL_WR(hcsp->Base + TUL_STimeOut, 153);
/* Enable Initiator Mode ,phase latch,alternate sync period mode,
disable SCSI reset */
if (hcsp->Config & HCC_EN_PAR)
TUL_WR(hcsp->Base + TUL_SConfig, TSC_INITDEFAULT | TSC_EN_SCSI_PAR);
else
TUL_WR(hcsp->Base + TUL_SConfig, TSC_INITDEFAULT );
post_scsi_rst(hcsp);
ScsiPortStallExecution(1000000); /* wait 1 sec */
return - 1; /* 07/31/97 */
}
/***************************************************************************/
char bad_seq(hcsp)
register HCS *hcsp;
{
register TULSCB *scbp;
if (scbp = hcsp->ActScb) {
ll_unlink_busy_scb(hcsp, scbp);
scbp->HaStat = HOST_BAD_PHAS;
scbp->TaStat = 0;
scbp->Status = TULSCB_DONE; /* done */
ll_append_done_scb(hcsp, scbp);
}
reset_scsi(hcsp);
return - 1;
}
/*******************reset_scsi for initialize ***************************/
void init_reset_scsi(hcsp)
register HCS *hcsp;
{
int i;
TCS * tcsp;
/* reset tulip chip */
TUL_WR( hcsp->Base + TUL_SCtrl0, TSC_RST_CHIP);
se2_wait(hcsp); /* wait 30 us */
TUL_WR( hcsp->Base + TUL_SIntEnable, 0xFF);
TUL_WR(hcsp->Base + TUL_SSignal, 0 );
/* if DMA xfer is pending, abort DMA xfer */
if (TUL_RD(hcsp->Base, TUL_XStatus) & XPEND) {
/* ----------- ABORT ----------------------*/
TUL_WR(hcsp->Base + TUL_XCmd, TAX_X_ABT | TAX_X_CLR_FIFO);
/* wait Abort DMA xfer done */
while ((TUL_RD(hcsp->Base, TUL_Int) & XABT) == 0)
;
}
/* Reset SCSI bus */
TUL_WR( hcsp->Base + TUL_SCtrl0, TSC_RST_BUS);
while ( (hcsp->JSInt = TUL_RD(hcsp->Base, TUL_SInt)) & TSS_SCSIRST_INT) {
}
ScsiPortStallExecution(10000000); /* wait 10 sec */
/* program HBA's SCSI ID */
TUL_WR( hcsp->Base + TUL_SScsiId, hcsp->HaId << 4);
if (hcsp->Config & HCC_EN_PAR)
TUL_WR(hcsp->Base + TUL_SConfig, TSC_INITDEFAULT | TSC_EN_SCSI_PAR);
else
TUL_WR(hcsp->Base + TUL_SConfig, TSC_INITDEFAULT );
/* Initialize the sync. xfer register values to an narrow, async. xfer */
TUL_WR(hcsp->Base + TUL_SPeriodOffset, 0x0);
/* selection time out = 250 ms */
TUL_WR(hcsp->Base + TUL_STimeOut, 153);
tcsp = &hcsp->Tcs[0];
for (i = 0; i < 16; tcsp++, i++) {
tcsp->Flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
} /* for */
// if (hwInitialized) {
post_scsi_rst(hcsp);
// }
}
/*******************reset_scsi rtn ***************************/
void reset_scsi(hcsp)
register HCS *hcsp;
{
int i;
TCS * tcsp;
/* reset tulip chip */
TUL_WR( hcsp->Base + TUL_SCtrl0, TSC_RST_CHIP);
se2_wait(hcsp); /* wait 30 us */
TUL_WR( hcsp->Base + TUL_SIntEnable, 0xFF);
TUL_WR(hcsp->Base + TUL_SSignal, 0 );
/* if DMA xfer is pending, abort DMA xfer */
if (TUL_RD(hcsp->Base, TUL_XStatus) & XPEND) {
/* ----------- ABORT ----------------------*/
TUL_WR(hcsp->Base + TUL_XCmd, TAX_X_ABT | TAX_X_CLR_FIFO);
/* wait Abort DMA xfer done */
while ((TUL_RD(hcsp->Base, TUL_Int) & XABT) == 0)
;
}
/* Reset SCSI bus */
TUL_WR( hcsp->Base + TUL_SCtrl0, TSC_RST_BUS);
while ( (hcsp->JSInt = TUL_RD(hcsp->Base, TUL_SInt)) & TSS_SCSIRST_INT) {
}
ScsiPortStallExecution(5000000); /* wait 5 sec */
/* program HBA's SCSI ID */
TUL_WR( hcsp->Base + TUL_SScsiId, hcsp->HaId << 4);
if (hcsp->Config & HCC_EN_PAR)
TUL_WR(hcsp->Base + TUL_SConfig, TSC_INITDEFAULT | TSC_EN_SCSI_PAR);
else
TUL_WR(hcsp->Base + TUL_SConfig, TSC_INITDEFAULT );
/* Initialize the sync. xfer register values to an narrow, async. xfer */
TUL_WR(hcsp->Base + TUL_SPeriodOffset, 0x0);
/* selection time out = 250 ms */
TUL_WR(hcsp->Base + TUL_STimeOut, 153);
tcsp = &hcsp->Tcs[0];
for (i = 0; i < 16; tcsp++, i++) {
tcsp->Flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
} /* for */
// if (hwInitialized) {
post_scsi_rst(hcsp);
// }
}
/***************************************************************************/
int post_scsi_rst(hcsp)
register HCS *hcsp;
{
register TULSCB *scbp;
int i;
while ((scbp = ll_pop_busy_scb(hcsp)) != NULL) {
scbp->Status = TULSCB_DONE;
scbp->HaStat = HOST_BAD_PHAS;
ll_append_done_scb(hcsp, scbp);
}
hcsp->ActScb = 0;
hcsp->NxtPend = 0;
hcsp->NxtContig = -1;
for (i = 0; i < 16; i++) {
hcsp->Tcs[i].Flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
}
return 1;
}
/***************************************************************************/
char msgout_abort(hcsp)
register HCS *hcsp;
{
char phase;
TUL_WR(hcsp->Base + TUL_SSignal,
(TUL_RD(hcsp->Base, TUL_SSignal) & 0x47) | TSC_SET_ATN);
if ( (phase = msg_accept(hcsp)) == -1)
return phase;
if (phase != MSG_OUT) {
return bad_seq(hcsp);
}
TUL_WR(hcsp->Base + TUL_SFifo, MSG_ABORT);
TUL_WR(hcsp->Base + TUL_SCmd, TSC_XF_FIFO_OUT);
hcsp->Flags |= HCF_EXPECT_DISC;
if (wait_tulip(hcsp) != -1) {
return bad_seq(hcsp);
}
return - 1;
}
/***************************************************************************/
char msgout_abort_tag(hcsp)
register HCS *hcsp;
{
char phase;
TUL_WR(hcsp->Base + TUL_SSignal,
(TUL_RD(hcsp->Base, TUL_SSignal) & 0x47) | TSC_SET_ATN);
if ( (phase = msg_accept(hcsp)) == -1)
return phase;
if (phase != MSG_OUT) {
return bad_seq(hcsp);
}
TUL_WR(hcsp->Base + TUL_SSignal,
(TUL_RD(hcsp->Base, TUL_SSignal) & 0x47));
TUL_WR(hcsp->Base + TUL_SFifo, MSG_ABORT_TAG);
TUL_WR(hcsp->Base + TUL_SCmd, TSC_XF_FIFO_OUT);
hcsp->Flags |= HCF_EXPECT_DISC;
if (wait_tulip(hcsp) != -1) {
return bad_seq(hcsp);
}
return - 1;
}
/**************** msgin rtn *******************************/
char msgin(hcsp, scbp)
register HCS *hcsp;
register TULSCB *scbp;
{
char phase;
UBYTE imsg, readByte;
ULONG_PTR TulSCmd;
register TCS *tcsp;
long cnt;
TulSCmd = hcsp->Base + TUL_SCmd;
if ( (cnt = TUL_RD(hcsp->Base, TUL_SFifoCnt) & 0x1F) != 0) {
readByte = TUL_RD(hcsp->Base, TUL_SSignal);
readByte &= 0x47; /* set BSYO,ATNO to 0,release ATN */
TUL_WR(hcsp->Base + TUL_SSignal, readByte);/* deassert ATN */
TUL_WR(hcsp->Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* flush SCSI FIFO */
}
for (; ; ) {
TUL_WRLONG(hcsp->Base + TUL_SCnt0, 1);
TUL_WR(TulSCmd, TSC_XF_FIFO_IN);
if ((phase = wait_tulip(hcsp)) == -1)
return - 1;
imsg = TUL_RD(hcsp->Base, TUL_SFifo);
switch (imsg) {
case MSG_DISC: /* Disconnect msg */
return msgin_discon(hcsp);
break;
case MSG_SDP:
case MSG_RESTORE:
case MSG_NOP:
phase = msg_accept(hcsp);
break;
case MSG_REJ:
tcsp = &hcsp->Tcs[scbp->Target];
if ( (tcsp->Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0) {
return msg_accept(hcsp);
}
phase = msg_accept(hcsp);
break;
case MSG_EXTEND: /* extended msg */
phase = msgin_extend(hcsp, scbp);
break;
case MSG_COMP:
hcsp->Flags |= HCF_EXPECT_DISC;
phase = msg_accept(hcsp);
ll_unlink_busy_scb(hcsp, hcsp->ActScb);
hcsp->ActScb->Status = TULSCB_DONE;
ll_append_done_scb(hcsp, hcsp->ActScb);
break;
default:
phase = msgout_reject(hcsp);
break;
}
if (phase != MSG_IN) {
return phase;
}
}
/* statement won't reach here */
}
/******************* msgin_discon rtn *******************/
char msgin_discon(hcsp)
register HCS *hcsp;
{
hcsp->Flags |= HCF_EXPECT_DISC;
return msg_accept(hcsp);
}
/************************ msgout_reject rtn ****************/
char msgout_reject(hcsp)
register HCS *hcsp;
{
char phase;
TUL_WR(hcsp->Base + TUL_SSignal,
(TUL_RD(hcsp->Base, TUL_SSignal) & 0x47) | TSC_SET_ATN);
if ( (phase = msg_accept(hcsp)) == -1) {
return phase;
}
if (phase == MSG_OUT) {
TUL_WR(hcsp->Base + TUL_SFifo, MSG_REJ); /* msg rej */
TUL_WR(hcsp->Base + TUL_SCmd, TSC_XF_FIFO_OUT);
return wait_tulip(hcsp);
}
return phase;
}
/************** msgout_sync rtn **************************/
int msgout_sync(hcsp)
register HCS *hcsp;
/* UBYTE msg[]; */
{
UCHAR xfrPeriod[8] = { /* fast 20 */
/* nanosecond devide by 4 */
12, /* 50ns, 20M */
18, /* 75ns, 13.3M */
25, /* 100ns, 10M */
31, /* 125ns, 8M */
37, /* 150ns, 6.6M */
43, /* 175ns, 5.7M */
50, /* 200ns, 5M */
62 /* 250ns, 4M */
};
char phase;
TUL_WR(hcsp->Base + TUL_SFifo, MSG_EXTEND);
TUL_WR(hcsp->Base + TUL_SFifo, 3);
TUL_WR(hcsp->Base + TUL_SFifo, 1);
TUL_WR(hcsp->Base + TUL_SFifo, xfrPeriod[hcsp->ActTcs->xfrPeriodIdx]);
TUL_WR(hcsp->Base + TUL_SFifo, MAX_OFFSET);
TUL_WR(hcsp->Base + TUL_SCmd,⌨️ 快捷键说明
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