uart_chen.tan.qmsg

来自「用VHDL语言编写的串口通讯器」· QMSG 代码 · 共 14 行 · 第 1/3 页

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "txclk " "Info: Detected ripple clock \"txclk\" as buffer" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 29 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "txclk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "mclkx16 register tsr\[7\] register txdone1 126.28 MHz 7.919 ns Internal " "Info: Clock \"mclkx16\" has Internal fmax of 126.28 MHz between source register \"tsr\[7\]\" and destination register \"txdone1\" (period= 7.919 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.212 ns + Longest register register " "Info: + Longest register to register delay is 3.212 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tsr\[7\] 1 REG LC_X24_Y15_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y15_N9; Fanout = 2; REG Node = 'tsr\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { tsr[7] } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.590 ns) 1.140 ns paritycycle~58 2 COMB LC_X24_Y15_N7 1 " "Info: 2: + IC(0.550 ns) + CELL(0.590 ns) = 1.140 ns; Loc. = LC_X24_Y15_N7; Fanout = 1; COMB Node = 'paritycycle~58'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.140 ns" { tsr[7] paritycycle~58 } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.292 ns) 1.894 ns paritycycle~6 3 COMB LC_X24_Y15_N0 3 " "Info: 3: + IC(0.462 ns) + CELL(0.292 ns) = 1.894 ns; Loc. = LC_X24_Y15_N0; Fanout = 3; COMB Node = 'paritycycle~6'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.754 ns" { paritycycle~58 paritycycle~6 } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.711 ns) + CELL(0.607 ns) 3.212 ns txdone1 4 REG LC_X23_Y15_N4 1 " "Info: 4: + IC(0.711 ns) + CELL(0.607 ns) = 3.212 ns; Loc. = LC_X23_Y15_N4; Fanout = 1; REG Node = 'txdone1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.318 ns" { paritycycle~6 txdone1 } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.489 ns ( 46.36 % ) " "Info: Total cell delay = 1.489 ns ( 46.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.723 ns ( 53.64 % ) " "Info: Total interconnect delay = 1.723 ns ( 53.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.212 ns" { tsr[7] paritycycle~58 paritycycle~6 txdone1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.212 ns" { tsr[7] {} paritycycle~58 {} paritycycle~6 {} txdone1 {} } { 0.000ns 0.550ns 0.462ns 0.711ns } { 0.000ns 0.590ns 0.292ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.446 ns - Smallest " "Info: - Smallest clock skew is -4.446 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclkx16 destination 2.962 ns + Shortest register " "Info: + Shortest clock path from clock \"mclkx16\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclkx16 1 CLK PIN_29 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 8; CLK Node = 'mclkx16'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mclkx16 } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns txdone1 2 REG LC_X23_Y15_N4 1 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X23_Y15_N4; Fanout = 1; REG Node = 'txdone1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { mclkx16 txdone1 } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { mclkx16 txdone1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { mclkx16 {} mclkx16~out0 {} txdone1 {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclkx16 source 7.408 ns - Longest register " "Info: - Longest clock path from clock \"mclkx16\" to source register is 7.408 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclkx16 1 CLK PIN_29 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 8; CLK Node = 'mclkx16'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mclkx16 } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns txclk 2 REG LC_X8_Y10_N2 13 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N2; Fanout = 13; REG Node = 'txclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { mclkx16 txclk } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.548 ns) + CELL(0.711 ns) 7.408 ns tsr\[7\] 3 REG LC_X24_Y15_N9 2 " "Info: 3: + IC(3.548 ns) + CELL(0.711 ns) = 7.408 ns; Loc. = LC_X24_Y15_N9; Fanout = 2; REG Node = 'tsr\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.259 ns" { txclk tsr[7] } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.05 % ) " "Info: Total cell delay = 3.115 ns ( 42.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.293 ns ( 57.95 % ) " "Info: Total interconnect delay = 4.293 ns ( 57.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.408 ns" { mclkx16 txclk tsr[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.408 ns" { mclkx16 {} mclkx16~out0 {} txclk {} tsr[7] {} } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { mclkx16 txdone1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { mclkx16 {} mclkx16~out0 {} txdone1 {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.408 ns" { mclkx16 txclk tsr[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.408 ns" { mclkx16 {} mclkx16~out0 {} txclk {} tsr[7] {} } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 78 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.212 ns" { tsr[7] paritycycle~58 paritycycle~6 txdone1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.212 ns" { tsr[7] {} paritycycle~58 {} paritycycle~6 {} txdone1 {} } { 0.000ns 0.550ns 0.462ns 0.711ns } { 0.000ns 0.590ns 0.292ns 0.607ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { mclkx16 txdone1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { mclkx16 {} mclkx16~out0 {} txdone1 {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.408 ns" { mclkx16 txclk tsr[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.408 ns" { mclkx16 {} mclkx16~out0 {} txclk {} tsr[7] {} } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "mclkx16 12 " "Warning: Circuit may not operate. Detected 12 non-operational path(s) clocked by clock \"mclkx16\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "txdatardy tsr\[2\] mclkx16 1.93 ns " "Info: Found hold time violation between source  pin or register \"txdatardy\" and destination pin or register \"tsr\[2\]\" for clock \"mclkx16\" (Hold time is 1.93 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.446 ns + Largest " "Info: + Largest clock skew is 4.446 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclkx16 destination 7.408 ns + Longest register " "Info: + Longest clock path from clock \"mclkx16\" to destination register is 7.408 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclkx16 1 CLK PIN_29 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 8; CLK Node = 'mclkx16'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mclkx16 } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns txclk 2 REG LC_X8_Y10_N2 13 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N2; Fanout = 13; REG Node = 'txclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { mclkx16 txclk } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.548 ns) + CELL(0.711 ns) 7.408 ns tsr\[2\] 3 REG LC_X24_Y15_N3 2 " "Info: 3: + IC(3.548 ns) + CELL(0.711 ns) = 7.408 ns; Loc. = LC_X24_Y15_N3; Fanout = 2; REG Node = 'tsr\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.259 ns" { txclk tsr[2] } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.05 % ) " "Info: Total cell delay = 3.115 ns ( 42.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.293 ns ( 57.95 % ) " "Info: Total interconnect delay = 4.293 ns ( 57.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.408 ns" { mclkx16 txclk tsr[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.408 ns" { mclkx16 {} mclkx16~out0 {} txclk {} tsr[2] {} } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclkx16 source 2.962 ns - Shortest register " "Info: - Shortest clock path from clock \"mclkx16\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclkx16 1 CLK PIN_29 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 8; CLK Node = 'mclkx16'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mclkx16 } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns txdatardy 2 REG LC_X24_Y15_N4 4 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X24_Y15_N4; Fanout = 4; REG Node = 'txdatardy'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { mclkx16 txdatardy } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { mclkx16 txdatardy } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { mclkx16 {} mclkx16~out0 {} txdatardy {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.408 ns" { mclkx16 txclk tsr[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.408 ns" { mclkx16 {} mclkx16~out0 {} txclk {} tsr[2] {} } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { mclkx16 txdatardy } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { mclkx16 {} mclkx16~out0 {} txdatardy {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 31 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.307 ns - Shortest register register " "Info: - Shortest register to register delay is 2.307 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns txdatardy 1 REG LC_X24_Y15_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y15_N4; Fanout = 4; REG Node = 'txdatardy'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { txdatardy } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.193 ns) + CELL(0.292 ns) 1.485 ns shift_out~0 2 COMB LC_X24_Y15_N1 12 " "Info: 2: + IC(1.193 ns) + CELL(0.292 ns) = 1.485 ns; Loc. = LC_X24_Y15_N1; Fanout = 12; COMB Node = 'shift_out~0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { txdatardy shift_out~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.513 ns) + CELL(0.309 ns) 2.307 ns tsr\[2\] 3 REG LC_X24_Y15_N3 2 " "Info: 3: + IC(0.513 ns) + CELL(0.309 ns) = 2.307 ns; Loc. = LC_X24_Y15_N3; Fanout = 2; REG Node = 'tsr\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.822 ns" { shift_out~0 tsr[2] } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.601 ns ( 26.05 % ) " "Info: Total cell delay = 0.601 ns ( 26.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.706 ns ( 73.95 % ) " "Info: Total interconnect delay = 1.706 ns ( 73.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.307 ns" { txdatardy shift_out~0 tsr[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.307 ns" { txdatardy {} shift_out~0 {} tsr[2] {} } { 0.000ns 1.193ns 0.513ns } { 0.000ns 0.292ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 78 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.408 ns" { mclkx16 txclk tsr[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.408 ns" { mclkx16 {} mclkx16~out0 {} txclk {} tsr[2] {} } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { mclkx16 txdatardy } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { mclkx16 {} mclkx16~out0 {} txdatardy {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.307 ns" { txdatardy shift_out~0 tsr[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.307 ns" { txdatardy {} shift_out~0 {} tsr[2] {} } { 0.000ns 1.193ns 0.513ns } { 0.000ns 0.292ns 0.309ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "thr\[4\] data\[4\] write 6.406 ns register " "Info: tsu for register \"thr\[4\]\" (data pin = \"data\[4\]\", clock pin = \"write\") is 6.406 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.693 ns + Longest pin register " "Info: + Longest pin to register delay is 8.693 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns data\[4\] 1 PIN PIN_95 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_95; Fanout = 1; PIN Node = 'data\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[4] } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.628 ns) + CELL(0.590 ns) 8.693 ns thr\[4\] 2 REG LC_X23_Y14_N3 1 " "Info: 2: + IC(6.628 ns) + CELL(0.590 ns) = 8.693 ns; Loc. = LC_X23_Y14_N3; Fanout = 1; REG Node = 'thr\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.218 ns" { data[4] thr[4] } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.065 ns ( 23.75 % ) " "Info: Total cell delay = 2.065 ns ( 23.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.628 ns ( 76.25 % ) " "Info: Total interconnect delay = 6.628 ns ( 76.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.693 ns" { data[4] thr[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.693 ns" { data[4] {} data[4]~out0 {} thr[4] {} } { 0.000ns 0.000ns 6.628ns } { 0.000ns 1.475ns 0.590ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.820 ns + " "Info: + Micro setup delay of destination is 0.820 ns" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "write destination 3.107 ns - Shortest register " "Info: - Shortest clock path from clock \"write\" to destination register is 3.107 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns write 1 CLK PIN_28 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 9; CLK Node = 'write'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { write } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.346 ns) + CELL(0.292 ns) 3.107 ns thr\[4\] 2 REG LC_X23_Y14_N3 1 " "Info: 2: + IC(1.346 ns) + CELL(0.292 ns) = 3.107 ns; Loc. = LC_X23_Y14_N3; Fanout = 1; REG Node = 'thr\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.638 ns" { write thr[4] } "NODE_NAME" } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.761 ns ( 56.68 % ) " "Info: Total cell delay = 1.761 ns ( 56.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.346 ns ( 43.32 % ) " "Info: Total interconnect delay = 1.346 ns ( 43.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.107 ns" { write thr[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.107 ns" { write {} write~out0 {} thr[4] {} } { 0.000ns 0.000ns 1.346ns } { 0.000ns 1.469ns 0.292ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.693 ns" { data[4] thr[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.693 ns" { data[4] {} data[4]~out0 {} thr[4] {} } { 0.000ns 0.000ns 6.628ns } { 0.000ns 1.475ns 0.590ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.107 ns" { write thr[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.107 ns" { write {} write~out0 {} thr[4] {} } { 0.000ns 0.000ns 1.346ns } { 0.000ns 1.469ns 0.292ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}