uart_chen.tan.qmsg

来自「用VHDL语言编写的串口通讯器」· QMSG 代码 · 共 14 行 · 第 1/3 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 10 16:54:34 2008 " "Info: Processing started: Thu Apr 10 16:54:34 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off uart_chen -c uart_chen --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off uart_chen -c uart_chen --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "thr\[1\] " "Warning: Node \"thr\[1\]\" is a latch" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "thr\[0\] " "Warning: Node \"thr\[0\]\" is a latch" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "thr\[2\] " "Warning: Node \"thr\[2\]\" is a latch" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "thr\[3\] " "Warning: Node \"thr\[3\]\" is a latch" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "thr\[4\] " "Warning: Node \"thr\[4\]\" is a latch" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "thr\[5\] " "Warning: Node \"thr\[5\]\" is a latch" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "thr\[6\] " "Warning: Node \"thr\[6\]\" is a latch" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "thr\[7\] " "Warning: Node \"thr\[7\]\" is a latch" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "mclkx16 " "Info: Assuming node \"mclkx16\" is an undefined clock" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 16 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "mclkx16" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "write " "Info: Assuming node \"write\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 16 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}