uart_chen.fnsim.qmsg

来自「用VHDL语言编写的串口通讯器」· QMSG 代码 · 共 35 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 10 09:44:30 2008 " "Info: Processing started: Thu Apr 10 09:44:30 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off uart_chen -c uart_chen --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart_chen -c uart_chen --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file uart.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 uart-top " "Info: Found design unit 1: uart-top" {  } { { "uart.vhd" "" { Text "F:/temp/UART_VHDL/uart.vhd" 29 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 uart " "Info: Found entity 1: uart" {  } { { "uart.vhd" "" { Text "F:/temp/UART_VHDL/uart.vhd" 13 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "F:/temp/UART_VHDL/Block1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rxcver.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rxcver.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rxcver-behave " "Info: Found design unit 1: rxcver-behave" {  } { { "rxcver.vhd" "" { Text "F:/temp/UART_VHDL/rxcver.vhd" 32 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 rxcver " "Info: Found entity 1: rxcver" {  } { { "rxcver.vhd" "" { Text "F:/temp/UART_VHDL/rxcver.vhd" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "txmit.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file txmit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 txmit-behave " "Info: Found design unit 1: txmit-behave" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 22 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 txmit " "Info: Found entity 1: txmit" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "txmit " "Info: Elaborating entity \"txmit\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "thr txmit.vhd(52) " "Warning (10631): VHDL Process Statement warning at txmit.vhd(52): inferring latch(es) for signal or variable \"thr\", which holds its previous value in one or more paths through the process" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "thr\[0\] txmit.vhd(52) " "Info (10041): Inferred latch for \"thr\[0\]\" at txmit.vhd(52)" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "thr\[1\] txmit.vhd(52) " "Info (10041): Inferred latch for \"thr\[1\]\" at txmit.vhd(52)" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "thr\[2\] txmit.vhd(52) " "Info (10041): Inferred latch for \"thr\[2\]\" at txmit.vhd(52)" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "thr\[3\] txmit.vhd(52) " "Info (10041): Inferred latch for \"thr\[3\]\" at txmit.vhd(52)" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "thr\[4\] txmit.vhd(52) " "Info (10041): Inferred latch for \"thr\[4\]\" at txmit.vhd(52)" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "thr\[5\] txmit.vhd(52) " "Info (10041): Inferred latch for \"thr\[5\]\" at txmit.vhd(52)" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "thr\[6\] txmit.vhd(52) " "Info (10041): Inferred latch for \"thr\[6\]\" at txmit.vhd(52)" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "thr\[7\] txmit.vhd(52) " "Info (10041): Inferred latch for \"thr\[7\]\" at txmit.vhd(52)" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" {  } { { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add0" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0}