uart_chen.map.qmsg

用VHDL语言编写的串口通讯器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 10 16:53:45 2008 " "Info: Processing started: Thu Apr 10 16:53:45 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off uart_chen -c uart_chen " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart_chen -c uart_chen" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file uart.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 uart-top " "Info: Found design unit 1: uart-top" {  } { { "uart.vhd" "" { Text "F:/temp/UART_VHDL/uart.vhd" 29 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 uart " "Info: Found entity 1: uart" {  } { { "uart.vhd" "" { Text "F:/temp/UART_VHDL/uart.vhd" 13 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "F:/temp/UART_VHDL/Block1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rxcver.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rxcver.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rxcver-behave " "Info: Found design unit 1: rxcver-behave" {  } { { "rxcver.vhd" "" { Text "F:/temp/UART_VHDL/rxcver.vhd" 32 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 rxcver " "Info: Found entity 1: rxcver" {  } { { "rxcver.vhd" "" { Text "F:/temp/UART_VHDL/rxcver.vhd" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "txmit.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file txmit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 txmit-behave " "Info: Found design unit 1: txmit-behave" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 22 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 txmit " "Info: Found entity 1: txmit" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "txmit " "Info: Elaborating entity \"txmit\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "thr txmit.vhd(52) " "Warning (10631): VHDL Process Statement warning at txmit.vhd(52): inferring latch(es) for signal or variable \"thr\", which holds its previous value in one or more paths through the process" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "thr\[0\] txmit.vhd(52) " "Info (10041): Inferred latch for \"thr\[0\]\" at txmit.vhd(52)" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "thr\[1\] txmit.vhd(52) " "Info (10041): Inferred latch for \"thr\[1\]\" at txmit.vhd(52)" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "thr\[2\] txmit.vhd(52) " "Info (10041): Inferred latch for \"thr\[2\]\" at txmit.vhd(52)" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "thr\[3\] txmit.vhd(52) " "Info (10041): Inferred latch for \"thr\[3\]\" at txmit.vhd(52)" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "thr\[4\] txmit.vhd(52) " "Info (10041): Inferred latch for \"thr\[4\]\" at txmit.vhd(52)" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "thr\[5\] txmit.vhd(52) " "Info (10041): Inferred latch for \"thr\[5\]\" at txmit.vhd(52)" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "thr\[6\] txmit.vhd(52) " "Info (10041): Inferred latch for \"thr\[6\]\" at txmit.vhd(52)" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "thr\[7\] txmit.vhd(52) " "Info (10041): Inferred latch for \"thr\[7\]\" at txmit.vhd(52)" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 18 -1 0 } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 28 -1 0 } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 24 -1 0 } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 23 -1 0 } } { "txmit.vhd" "" { Text "F:/temp/UART_VHDL/txmit.vhd" 23 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "47 " "Info: Implemented 47 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "34 " "Info: Implemented 34 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "159 " "Info: Allocated 159 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 10 16:53:58 2008 " "Info: Processing ended: Thu Apr 10 16:53:58 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}