uart_chen.hier_info

用VHDL语言编写的串口通讯器

|txmit
mclkx16 => txclk.CLK
mclkx16 => cnt[2].CLK
mclkx16 => cnt[1].CLK
mclkx16 => cnt[0].CLK
mclkx16 => txdatardy.CLK
mclkx16 => write2.CLK
mclkx16 => write1.CLK
mclkx16 => txdone1.CLK
write => write1.DATAIN
write => thr[7].LATCH_ENABLE
write => thr[6].LATCH_ENABLE
write => thr[5].LATCH_ENABLE
write => thr[4].LATCH_ENABLE
write => thr[3].LATCH_ENABLE
write => thr[2].LATCH_ENABLE
write => thr[1].LATCH_ENABLE
write => thr[0].LATCH_ENABLE
reset => txclk.ACLR
reset => cnt[2].ACLR
reset => cnt[1].ACLR
reset => cnt[0].ACLR
reset => tsr[7].ACLR
reset => tsr[6].ACLR
reset => tsr[5].ACLR
reset => tsr[4].ACLR
reset => tsr[3].ACLR
reset => tsr[2].ACLR
reset => tsr[1].ACLR
reset => tsr[0].ACLR
reset => tag2.ACLR
reset => tag1.ACLR
reset => txparity.PRESET
reset => tx~reg0.PRESET
reset => txdatardy.ACLR
reset => write2.PRESET
reset => write1.PRESET
reset => txdone1.PRESET
data[0] => thr[0].DATAIN
data[1] => thr[1].DATAIN
data[2] => thr[2].DATAIN
data[3] => thr[3].DATAIN
data[4] => thr[4].DATAIN
data[5] => thr[5].DATAIN
data[6] => thr[6].DATAIN
data[7] => thr[7].DATAIN
tx <= tx~reg0.DB_MAX_OUTPUT_PORT_TYPE
txrdy <= txdatardy.DB_MAX_OUTPUT_PORT_TYPE