uart.tf

用VHDL语言编写的串口通讯器

/*******************************************************************
 *
 *    DESCRIPTION: UART test-fixture
 *
 *    AUTHOR: Thomas Oelsner
 *
 *    HISTORY: 10/04/96, 
 *
 *		DESCRIPTION:  	The test-fixture loops back the tx output to the rx input.
 *						  	Within a for loop, the test-fixture writes all possible data combinations
 *						  	to the transmitter. Data gets received by the receiver and compared to the data that
 *							what send. 
 *
 *******************************************************************/
`timescale 1ns/1ps

module t;

reg 			mclkx16, read, write, rx, reset;
wire 			[7:0] data;
wire 			tx, rxrdy, txrdy, parityerr, framingerr, overrun;


parameter	baudrate = 500;	// Specify in [nS] the baudrate for the simulation.
  
integer		i;
reg			[7:0] data_received, data_written;


// Instantiate UART top level module into test-fixture.	
    uart m (.mclkx16(mclkx16), .reset(reset), .read(read), .write(write), .data(data), 
				.rx(rx), .tx(tx), .rxrdy(rxrdy), .txrdy(txrdy), .parityerr(parityerr), .framingerr(framingerr), .overrun(overrun));


// Generate 16 times baudrate clock frequency, i.e. Baudrate = mclkx16/16.
initial begin
   mclkx16 = 1;
   forever begin
      #(baudrate/(16*2));			// Divide baudrate periode by 32 to get half mclkx16 periode. 
      mclkx16 = ~mclkx16;
      end
end

// Reset UART. 
initial begin
   reset = 1; #2000;
   reset = 0;
   end


//Feeding back transmit output to receive input
always @(tx) 
	begin
		#1;			
		rx = tx;
	end	



// Task for writing data to transmitter.
// Timing can be modified in order to model any cpu write cycle.
task write_to_transmitter;
	input [7:0] din;
	begin
   	write = 0;
		#100;
		force data = din;
   	#50;						
   	write = 1;
		data_written = din;		// Latch contents of data bus.	 
		#20;
		release data;
	end
endtask


// Task for reading out data from receiver.
// Timing can be modified in order to model any cpu read cycle.
task read_out_receiver;
	begin
		read = 0;		
		#25;
		data_received = data;		// Latch contents of data bus.	
		#75;
		read = 1;
	end
endtask //



// Compares data send & data received, and flags for error if any occures.
// Comparation is done just previous to next data transmission, and after
// previous received data has been read out.
task compare_data;
	begin
	if (data_written !== data_received) begin
					  $display("\n");
					  $display("	FAILED at time = %3d ns", $time);
					  $display("	Value of data transmitted = %3H --> data received = %3H", data_written, data_received);     
					  $stop;
					  end
	end
endtask //


// Here begins the core test program.
initial begin
	write = 1;							// de-assert write initially. 
	read = 1;							// de-assert read initially.
	#100;
	force t.rxrdy = 0;	#50;		// Necessary for proper initialisation.
	release t.rxrdy;
	#2300;								// Wait for reset to go low.

	// Write every possible combinations to the transmitter.
	for (i = 8'h0; i  <= 8'hff; i = i + 1) begin
		write_to_transmitter(i);		// Write new data to transmitter.
		wait(rxrdy);						// Wait for rxrdy.
		read_out_receiver;				// Read out data from receiver.
		compare_data;						// Compare "data send" to "data received".
		end

	$display("\n");
	$display("************************************************************************");
	$display("\n");
	$display("*		Simulation OK, passed all posible combinations sucessfully");	 
	$display("\n");
	$display("************************************************************************");
	$stop;
	end

endmodule