uart_chen.tan.rpt

用VHDL语言编写的串口通讯器

Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Apr 10 16:54:34 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off uart_chen -c uart_chen --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "thr[1]" is a latch
    Warning: Node "thr[0]" is a latch
    Warning: Node "thr[2]" is a latch
    Warning: Node "thr[3]" is a latch
    Warning: Node "thr[4]" is a latch
    Warning: Node "thr[5]" is a latch
    Warning: Node "thr[6]" is a latch
    Warning: Node "thr[7]" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "mclkx16" is an undefined clock
    Info: Assuming node "write" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "txclk" as buffer
Info: Clock "mclkx16" has Internal fmax of 126.28 MHz between source register "tsr[7]" and destination register "txdone1" (period= 7.919 ns)
    Info: + Longest register to register delay is 3.212 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y15_N9; Fanout = 2; REG Node = 'tsr[7]'
        Info: 2: + IC(0.550 ns) + CELL(0.590 ns) = 1.140 ns; Loc. = LC_X24_Y15_N7; Fanout = 1; COMB Node = 'paritycycle~58'
        Info: 3: + IC(0.462 ns) + CELL(0.292 ns) = 1.894 ns; Loc. = LC_X24_Y15_N0; Fanout = 3; COMB Node = 'paritycycle~6'
        Info: 4: + IC(0.711 ns) + CELL(0.607 ns) = 3.212 ns; Loc. = LC_X23_Y15_N4; Fanout = 1; REG Node = 'txdone1'
        Info: Total cell delay = 1.489 ns ( 46.36 % )
        Info: Total interconnect delay = 1.723 ns ( 53.64 % )
    Info: - Smallest clock skew is -4.446 ns
        Info: + Shortest clock path from clock "mclkx16" to destination register is 2.962 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 8; CLK Node = 'mclkx16'
            Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X23_Y15_N4; Fanout = 1; REG Node = 'txdone1'
            Info: Total cell delay = 2.180 ns ( 73.60 % )
            Info: Total interconnect delay = 0.782 ns ( 26.40 % )
        Info: - Longest clock path from clock "mclkx16" to source register is 7.408 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 8; CLK Node = 'mclkx16'
            Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N2; Fanout = 13; REG Node = 'txclk'
            Info: 3: + IC(3.548 ns) + CELL(0.711 ns) = 7.408 ns; Loc. = LC_X24_Y15_N9; Fanout = 2; REG Node = 'tsr[7]'
            Info: Total cell delay = 3.115 ns ( 42.05 % )
            Info: Total interconnect delay = 4.293 ns ( 57.95 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Warning: Circuit may not operate. Detected 12 non-operational path(s) clocked by clock "mclkx16" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "txdatardy" and destination pin or register "tsr[2]" for clock "mclkx16" (Hold time is 1.93 ns)
    Info: + Largest clock skew is 4.446 ns
        Info: + Longest clock path from clock "mclkx16" to destination register is 7.408 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 8; CLK Node = 'mclkx16'
            Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N2; Fanout = 13; REG Node = 'txclk'
            Info: 3: + IC(3.548 ns) + CELL(0.711 ns) = 7.408 ns; Loc. = LC_X24_Y15_N3; Fanout = 2; REG Node = 'tsr[2]'
            Info: Total cell delay = 3.115 ns ( 42.05 % )
            Info: Total interconnect delay = 4.293 ns ( 57.95 % )
        Info: - Shortest clock path from clock "mclkx16" to source register is 2.962 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 8; CLK Node = 'mclkx16'
            Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X24_Y15_N4; Fanout = 4; REG Node = 'txdatardy'
            Info: Total cell delay = 2.180 ns ( 73.60 % )
            Info: Total interconnect delay = 0.782 ns ( 26.40 % )
    Info: - Micro clock to output delay of source is 0.224 ns
    Info: - Shortest register to register delay is 2.307 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y15_N4; Fanout = 4; REG Node = 'txdatardy'
        Info: 2: + IC(1.193 ns) + CELL(0.292 ns) = 1.485 ns; Loc. = LC_X24_Y15_N1; Fanout = 12; COMB Node = 'shift_out~0'
        Info: 3: + IC(0.513 ns) + CELL(0.309 ns) = 2.307 ns; Loc. = LC_X24_Y15_N3; Fanout = 2; REG Node = 'tsr[2]'
        Info: Total cell delay = 0.601 ns ( 26.05 % )
        Info: Total interconnect delay = 1.706 ns ( 73.95 % )
    Info: + Micro hold delay of destination is 0.015 ns
Info: tsu for register "thr[4]" (data pin = "data[4]", clock pin = "write") is 6.406 ns
    Info: + Longest pin to register delay is 8.693 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_95; Fanout = 1; PIN Node = 'data[4]'
        Info: 2: + IC(6.628 ns) + CELL(0.590 ns) = 8.693 ns; Loc. = LC_X23_Y14_N3; Fanout = 1; REG Node = 'thr[4]'
        Info: Total cell delay = 2.065 ns ( 23.75 % )
        Info: Total interconnect delay = 6.628 ns ( 76.25 % )
    Info: + Micro setup delay of destination is 0.820 ns
    Info: - Shortest clock path from clock "write" to destination register is 3.107 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 9; CLK Node = 'write'
        Info: 2: + IC(1.346 ns) + CELL(0.292 ns) = 3.107 ns; Loc. = LC_X23_Y14_N3; Fanout = 1; REG Node = 'thr[4]'
        Info: Total cell delay = 1.761 ns ( 56.68 % )
        Info: Total interconnect delay = 1.346 ns ( 43.32 % )
Info: tco from clock "mclkx16" to destination pin "tx" through register "tx~reg0" is 12.527 ns
    Info: + Longest clock path from clock "mclkx16" to source register is 7.408 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 8; CLK Node = 'mclkx16'
        Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N2; Fanout = 13; REG Node = 'txclk'
        Info: 3: + IC(3.548 ns) + CELL(0.711 ns) = 7.408 ns; Loc. = LC_X23_Y15_N2; Fanout = 1; REG Node = 'tx~reg0'
        Info: Total cell delay = 3.115 ns ( 42.05 % )
        Info: Total interconnect delay = 4.293 ns ( 57.95 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.895 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y15_N2; Fanout = 1; REG Node = 'tx~reg0'
        Info: 2: + IC(2.787 ns) + CELL(2.108 ns) = 4.895 ns; Loc. = PIN_213; Fanout = 0; PIN Node = 'tx'
        Info: Total cell delay = 2.108 ns ( 43.06 % )
        Info: Total interconnect delay = 2.787 ns ( 56.94 % )
Info: th for register "write1" (data pin = "write", clock pin = "mclkx16") is -0.321 ns
    Info: + Longest clock path from clock "mclkx16" to destination register is 2.962 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 8; CLK Node = 'mclkx16'
        Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X26_Y15_N4; Fanout = 2; REG Node = 'write1'
        Info: Total cell delay = 2.180 ns ( 73.60 % )
        Info: Total interconnect delay = 0.782 ns ( 26.40 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 3.298 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 9; CLK Node = 'write'
        Info: 2: + IC(1.351 ns) + CELL(0.478 ns) = 3.298 ns; Loc. = LC_X26_Y15_N4; Fanout = 2; REG Node = 'write1'
        Info: Total cell delay = 1.947 ns ( 59.04 % )
        Info: Total interconnect delay = 1.351 ns ( 40.96 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 12 warnings
    Info: Allocated 111 megabytes of memory during processing
    Info: Processing ended: Thu Apr 10 16:54:35 2008
    Info: Elapsed time: 00:00:01