uart.v

用VHDL语言编写的串口通讯器

/*******************************************************************
 *
 *    DESCRIPTION: UART top level module implements full duplex UART function.
 *
 *    AUTHOR: Thomas Oelsner
 *
 *    HISTORY: 10/04/96    
 *
 *******************************************************************/
//Includes Verilog HDL sources for Transmitter & receiver modules
`include "txmit.v"
`include "rxcver.v"

module uart (mclkx16, reset, read, write, data, rx, tx, rxrdy, txrdy, parityerr, framingerr, overrun);
                
input       mclkx16;		   // Input clock, 16 x baud rate clock used for synchronisation.
input       read;		      // read strobe input.
input       write;		   // write strobe input.
input	      reset;		   // Master reset input.

inout 		[7:0] data;		// Bidirectional data bus for writing to transmitter & reading from receiver.


// Receiver input signal, error and status flags.
input	      rx;		                        // Receive  data line input
output      rxrdy;      wire     rxrdy;      // Data ready to be read.
output      parityerr;  wire     parityerr;  // Parity error flag.
output      framingerr; wire     framingerr; // Framing error flag.
output      overrun;    wire     overrun;    // Overrun error flag. 
wire        [7:0] rxdata;		               // Intermediate output signals from receiver. 


// Transmitter output signal and status flag.
output      tx;         wire     tx;         // Transmit data line output
output      txrdy;      wire     txrdy;      // Transmitter ready for next byte.


//Instantiation of the transmitter module. 
txmit tx_1 (mclkx16, write, reset, tx, txrdy, data);


// Instantiation of the receiver module.
rxcver  rx_1 (mclkx16, read, rx, reset, rxrdy, parityerr, framingerr, overrun, rxdata);


//Drives the databus during data read, otherwise tri-state the data bus.
assign 		data = !read ? rxdata : 8'bzzzzzzzz;

endmodule