uart_chen.map.rpt

用VHDL语言编写的串口通讯器

+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 34    ;
;     -- Combinational with no register       ; 14    ;
;     -- Register only                        ; 2     ;
;     -- Combinational with a register        ; 18    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 6     ;
;     -- 3 input functions                    ; 20    ;
;     -- 2 input functions                    ; 4     ;
;     -- 1 input functions                    ; 2     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 34    ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 20    ;
;                                             ;       ;
; Total registers                             ; 20    ;
; I/O pins                                    ; 13    ;
; Maximum fan-out node                        ; reset ;
; Maximum fan-out                             ; 20    ;
; Total fan-out                               ; 138   ;
; Average fan-out                             ; 2.94  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |txmit                     ; 34 (34)     ; 20           ; 0           ; 13   ; 0            ; 14 (14)      ; 2 (2)             ; 18 (18)          ; 0 (0)           ; 0 (0)      ; |txmit              ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; thr[0]                                             ; write               ; yes                    ;
; thr[1]                                             ; write               ; yes                    ;
; thr[2]                                             ; write               ; yes                    ;
; thr[3]                                             ; write               ; yes                    ;
; thr[4]                                             ; write               ; yes                    ;
; thr[5]                                             ; write               ; yes                    ;
; thr[6]                                             ; write               ; yes                    ;
; thr[7]                                             ; write               ; yes                    ;
; Number of user-specified and inferred latches = 8  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 20    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 20    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; tx~reg0                                ; 1       ;
; txparity                               ; 2       ;
; txdone1                                ; 1       ;
; write2                                 ; 1       ;
; write1                                 ; 2       ;
; Total number of inverted registers = 5 ;         ;
+----------------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Apr 10 16:53:45 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart_chen -c uart_chen
Info: Found 2 design units, including 1 entities, in source file uart.vhd
    Info: Found design unit 1: uart-top
    Info: Found entity 1: uart
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
    Info: Found entity 1: Block1
Info: Found 2 design units, including 1 entities, in source file rxcver.vhd
    Info: Found design unit 1: rxcver-behave
    Info: Found entity 1: rxcver
Info: Found 2 design units, including 1 entities, in source file txmit.vhd
    Info: Found design unit 1: txmit-behave
    Info: Found entity 1: txmit
Info: Elaborating entity "txmit" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at txmit.vhd(52): inferring latch(es) for signal or variable "thr", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "thr[0]" at txmit.vhd(52)
Info (10041): Inferred latch for "thr[1]" at txmit.vhd(52)
Info (10041): Inferred latch for "thr[2]" at txmit.vhd(52)
Info (10041): Inferred latch for "thr[3]" at txmit.vhd(52)
Info (10041): Inferred latch for "thr[4]" at txmit.vhd(52)
Info (10041): Inferred latch for "thr[5]" at txmit.vhd(52)
Info (10041): Inferred latch for "thr[6]" at txmit.vhd(52)
Info (10041): Inferred latch for "thr[7]" at txmit.vhd(52)
Info: Registers with preset signals will power-up high
Info: Implemented 47 device resources after synthesis - the final resource count might be different
    Info: Implemented 11 input pins
    Info: Implemented 2 output pins
    Info: Implemented 34 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Allocated 159 megabytes of memory during processing
    Info: Processing ended: Thu Apr 10 16:53:58 2008
    Info: Elapsed time: 00:00:13