5566

用VHDL语言编写的串口通讯器

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.


-- Generated by Quartus II Version 7.2 (Build Build 151 09/26/2007)
-- Created on Wed Apr 09 16:27:36 2008

LIBRARY ieee;
USE ieee.std_logic_1164.all;


--  Entity Declaration

ENTITY conter IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		clk : IN STD_LOGIC;
		clr : IN STD_LOGIC;
		ld : IN STD_LOGIC;
		m : IN STD_LOGIC_VECTOR(6 downto 0);
		q : OUT STD_LOGIC_VECTOR(6 downto 0)
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END conter;


--  Architecture Body

ARCHITECTURE conter_architecture OF conter IS

	
BEGIN

END conter_architecture;