sfr62p.h

renesas m16c DMA data access sample the whole project is tested in HEW,and works corectly.

#define		ifsr0			ifsr_addr.bit.b0	/* INT0~ interrupt polarity switching bit */
#define		ifsr1			ifsr_addr.bit.b1	/* INT1~ interrupt polarity switching bit */
#define		ifsr2			ifsr_addr.bit.b2	/* INT2~ interrupt polarity switching bit */
#define		ifsr3			ifsr_addr.bit.b3	/* INT3~ interrupt polarity switching bit */
#define		ifsr4			ifsr_addr.bit.b4	/* INT4~ interrupt polarity switching bit */
#define		ifsr5			ifsr_addr.bit.b5	/* INT5~ interrupt polarity switching bit */
#define		ifsr6			ifsr_addr.bit.b6	/* Interrupt request cause select bit */
#define		ifsr7			ifsr_addr.bit.b7	/* Interrupt request cause select bit */

/*------------------------------------------------------
	SI/O3 transmit/receive register
------------------------------------------------------*/
union byte_def s3trr_addr;
#define		s3trr			s3trr_addr.byte

/*------------------------------------------------------
	SI/O3 control register 
------------------------------------------------------*/
union byte_def s3c_addr;
#define		s3c				s3c_addr.byte

#define		sm30			s3c_addr.bit.b0		/* Internal synchronous clock select bit */
#define		sm31			s3c_addr.bit.b1		/* Internal synchronous clock select bit */
#define		sm32			s3c_addr.bit.b2		/* Sout3 output disable bit */
#define		sm33			s3c_addr.bit.b3		/* SI/O3 port select bit */
#define		sm34			s3c_addr.bit.b4		/* CLK polarity select bit */
#define		sm35			s3c_addr.bit.b5		/* Transfer direction select bit */
#define		sm36			s3c_addr.bit.b6		/* Synchronous clock select bit */
#define		sm37			s3c_addr.bit.b7		/* Sout3 initial value set bit */

/*------------------------------------------------------
	SI/O3 bit rate generator ; Use "MOV" instruction when writing to this register.
------------------------------------------------------*/
union byte_def s3brg_addr;
#define		s3brg			s3brg_addr.byte

/*------------------------------------------------------
	SI/O4 transmit/receive register
------------------------------------------------------*/
union byte_def s4trr_addr;
#define		s4trr			s4trr_addr.byte

/*------------------------------------------------------
	SI/O4 control register 
------------------------------------------------------*/
union byte_def s4c_addr;
#define		s4c				s4c_addr.byte

#define		sm40			s4c_addr.bit.b0		/* Internal synchronous clock select bit */
#define		sm41			s4c_addr.bit.b1		/* Internal synchronous clock select bit */
#define		sm42			s4c_addr.bit.b2		/* Sout4 output disable bit */
#define		sm43			s4c_addr.bit.b3		/* SI/O4 port select bit */
#define		sm44			s4c_addr.bit.b4		/* CLK polarity select bit */
#define		sm45			s4c_addr.bit.b5		/* Transfer direction select bit */
#define		sm46			s4c_addr.bit.b6		/* Synchronous clock select bit */
#define		sm47			s4c_addr.bit.b7		/* Sout4 initial value set bit */

/*------------------------------------------------------
	SI/O4 bit rate generator ; Use "MOV" instruction when writing to this register.
------------------------------------------------------*/
union byte_def s4brg_addr;
#define		s4brg			s4brg_addr.byte

/*------------------------------------------------------
	UART0 special mode register 4
------------------------------------------------------*/
union byte_def u0smr4_addr;
#define		u0smr4			u0smr4_addr.byte

#define		stareq_u0smr4	u0smr4_addr.bit.b0	/* Start condition generate bit */
#define		rstareq_u0smr4	u0smr4_addr.bit.b1	/* Restart condition generate bit */
#define		stpreq_u0smr4	u0smr4_addr.bit.b2	/* Stop condition generate bit */
#define		stspsel_u0smr4	u0smr4_addr.bit.b3	/* SCL,SDA output select bit */
#define		ackd_u0smr4		u0smr4_addr.bit.b4	/* ACK data bit */
#define		ackc_u0smr4		u0smr4_addr.bit.b5	/* ACK data output enable bit */
#define		sclhi_u0smr4	u0smr4_addr.bit.b6	/* SCL output stop enable bit */
#define		swc9_u0smr4		u0smr4_addr.bit.b7	/* Final bit L hold enable bit */

/*------------------------------------------------------
	UART0 special mode register 3
------------------------------------------------------*/
union byte_def u0smr3_addr;
#define		u0smr3			u0smr3_addr.byte

#define		ckph_u0smr3		u0smr3_addr.bit.b1	/* Clock phase set bit */
#define		nodc_u0smr3		u0smr3_addr.bit.b3	/* Clock output set bit */
#define		dl0_u0smr3		u0smr3_addr.bit.b5	/* SDA0(TxD0) digital delay setup bit */
#define		dl1_u0smr3		u0smr3_addr.bit.b6	/* SDA0(TxD0) digital delay setup bit */
#define		dl2_u0smr3		u0smr3_addr.bit.b7	/* SDA0(TxD0) digital delay setup bit */

/*------------------------------------------------------
	UART0 special mode register 2
------------------------------------------------------*/
union byte_def u0smr2_addr;
#define		u0smr2			u0smr2_addr.byte

#define		iicm2_u0smr2	u0smr2_addr.bit.b0	/* IIC mode selection bit 2 */
#define		csc_u0smr2		u0smr2_addr.bit.b1	/* Clock-synchronous bit */
#define		swc_u0smr2		u0smr2_addr.bit.b2	/* SCL wait output bit */
#define		als_u0smr2		u0smr2_addr.bit.b3	/* SDA output stop bit */
#define		stac_u0smr2		u0smr2_addr.bit.b4	/* UART0 initialization bit */
#define		swc2_u0smr2		u0smr2_addr.bit.b5	/* SCL wait output bit 2 */
#define		sdhi_u0smr2		u0smr2_addr.bit.b6	/* SDA output disable bit */

/*------------------------------------------------------
	UART0 special mode register
------------------------------------------------------*/
union byte_def u0smr_addr;
#define		u0smr			u0smr_addr.byte

#define		iicm_u0smr		u0smr_addr.bit.b0	/* IIC mode selection bit */
#define		abc_u0smr		u0smr_addr.bit.b1	/* Arbitration lost detecting flag control bit */
#define		bbs_u0smr		u0smr_addr.bit.b2	/* Bus busy flag */
#define		lsyn_u0smr		u0smr_addr.bit.b3	/* SCLL sync output enable bit */
#define		abscs_u0smr		u0smr_addr.bit.b4	/* Bus collision detect sampling clock select bit */
#define		acse_u0smr		u0smr_addr.bit.b5	/* Auto clear function select bit of transmit enable bit */
#define		sss_u0smr		u0smr_addr.bit.b6	/* Transmit start condition select bit */

/*------------------------------------------------------
	UART1 special mode register 4
------------------------------------------------------*/
union byte_def u1smr4_addr;
#define		u1smr4			u1smr4_addr.byte

#define		stareq_u1smr4	u1smr4_addr.bit.b0	/* Start condition generate bit */
#define		rstareq_u1smr4	u1smr4_addr.bit.b1	/* Restart condition generate bit */
#define		stpreq_u1smr4	u1smr4_addr.bit.b2	/* Stop condition generate bit */
#define		stspsel_u1smr4	u1smr4_addr.bit.b3	/* SCL,SDA output select bit */
#define		ackd_u1smr4		u1smr4_addr.bit.b4	/* ACK data bit */
#define		ackc_u1smr4		u1smr4_addr.bit.b5	/* ACK data output enable bit */
#define		sclhi_u1smr4	u1smr4_addr.bit.b6	/* SCL output stop enable bit */
#define		swc9_u1smr4		u1smr4_addr.bit.b7	/* Final bit L hold enable bit */

/*------------------------------------------------------
	UART1 special mode register 3
------------------------------------------------------*/
union byte_def u1smr3_addr;
#define		u1smr3			u1smr3_addr.byte

#define		ckph_u1smr3		u1smr3_addr.bit.b1	/* Clock phase set bit */
#define		nodc_u1smr3		u1smr3_addr.bit.b3	/* Clock output set bit */
#define		dl0_u1smr3		u1smr3_addr.bit.b5	/* SDA1(TxD1) digital delay setup bit */
#define		dl1_u1smr3		u1smr3_addr.bit.b6	/* SDA1(TxD1) digital delay setup bit */
#define		dl2_u1smr3		u1smr3_addr.bit.b7	/* SDA1(TxD1) digital delay setup bit */

/*------------------------------------------------------
	UART1 special mode register 2
------------------------------------------------------*/
union byte_def u1smr2_addr;
#define		u1smr2			u1smr2_addr.byte

#define		iicm2_u1smr2	u1smr2_addr.bit.b0	/* IIC mode selection bit 2 */
#define		csc_u1smr2		u1smr2_addr.bit.b1	/* Clock-synchronous bit */
#define		swc_u1smr2		u1smr2_addr.bit.b2	/* SCL wait output bit */
#define		als_u1smr2		u1smr2_addr.bit.b3	/* SDA output stop bit */
#define		stac_u1smr2		u1smr2_addr.bit.b4	/* UART0 initialization bit */
#define		swc2_u1smr2		u1smr2_addr.bit.b5	/* SCL wait output bit 2 */
#define		sdhi_u1smr2		u1smr2_addr.bit.b6	/* SDA output disable bit */

/*------------------------------------------------------
	UART1 special mode register
------------------------------------------------------*/
union byte_def u1smr_addr;
#define		u1smr			u1smr_addr.byte

#define		iicm_u1smr		u1smr_addr.bit.b0	/* IIC mode selection bit */
#define		abc_u1smr		u1smr_addr.bit.b1	/* Arbitration lost detecting flag control bit */
#define		bbs_u1smr		u1smr_addr.bit.b2	/* Bus busy flag */
#define		lsyn_u1smr		u1smr_addr.bit.b3	/* SCLL sync output enable bit */
#define		abscs_u1smr		u1smr_addr.bit.b4	/* Bus collision detect sampling clock select bit */
#define		acse_u1smr		u1smr_addr.bit.b5	/* Auto clear function select bit of transmit enable bit */
#define		sss_u1smr		u1smr_addr.bit.b6	/* Transmit start condition select bit */

/*------------------------------------------------------
	UART2 special mode register 4
------------------------------------------------------*/
union byte_def u2smr4_addr;
#define		u2smr4			u2smr4_addr.byte

#define		stareq_u2smr4	u2smr4_addr.bit.b0	/* Start condition generate bit */
#define		rstareq_u2smr4	u2smr4_addr.bit.b1	/* Restart condition generate bit */
#define		stpreq_u2smr4	u2smr4_addr.bit.b2	/* Stop condition generate bit */
#define		stspsel_u2smr4	u2smr4_addr.bit.b3	/* SCL,SDA output select bit */
#define		ackd_u2smr4		u2smr4_addr.bit.b4	/* ACK data bit */
#define		ackc_u2smr4		u2smr4_addr.bit.b5	/* ACK data output enable bit */
#define		sclhi_u2smr4	u2smr4_addr.bit.b6	/* SCL output stop enable bit */
#define		swc9_u2smr4		u2smr4_addr.bit.b7	/* Final bit L hold enable bit */

/*------------------------------------------------------
	UART2 special mode register 3
------------------------------------------------------*/
union byte_def u2smr3_addr;
#define		u2smr3			u2smr3_addr.byte

#define		ckph_u2smr3		u2smr3_addr.bit.b1	/* Clock phase set bit */
#define		nodc_u2smr3		u2smr3_addr.bit.b3	/* Clock output set bit */
#define		dl0_u2smr3		u2smr3_addr.bit.b5	/* SDA2(TxD2) digital delay setup bit */
#define		dl1_u2smr3		u2smr3_addr.bit.b6	/* SDA2(TxD2) digital delay setup bit */
#define		dl2_u2smr3		u2smr3_addr.bit.b7	/* SDA2(TxD2) digital delay setup bit */

/*------------------------------------------------------
	UART2 special mode register 2
------------------------------------------------------*/
union byte_def u2smr2_addr;
#define		u2smr2			u2smr2_addr.byte

#define		iicm2_u2smr2	u2smr2_addr.bit.b0	/* IIC mode selection bit 2 */
#define		csc_u2smr2		u2smr2_addr.bit.b1	/* Clock-synchronous bit */
#define		swc_u2smr2		u2smr2_addr.bit.b2	/* SCL wait output bit */
#define		als_u2smr2		u2smr2_addr.bit.b3	/* SDA output stop bit */
#define		stac_u2smr2		u2smr2_addr.bit.b4	/* UART0 initialization bit */
#define		swc2_u2smr2		u2smr2_addr.bit.b5	/* SCL wait output bit 2 */
#define		sdhi_u2smr2		u2smr2_addr.bit.b6	/* SDA output disable bit */

/*------------------------------------------------------
	UART2 special mode register
------------------------------------------------------*/
union byte_def u2smr_addr;
#define		u2smr			u2smr_addr.byte

#define		iicm_u2smr		u2smr_addr.bit.b0	/* IIC mode selection bit */
#define		abc_u2smr		u2smr_addr.bit.b1	/* Arbitration lost detecting flag control bit */
#define		bbs_u2smr		u2smr_addr.bit.b2	/* Bus busy flag */
#define		lsyn_u2smr		u2smr_addr.bit.b3	/* SCLL sync output enable bit */
#define		abscs_u2smr		u2smr_addr.bit.b4	/* Bus collision detect sampling clock select bit */
#define		acse_u2smr		u2smr_addr.bit.b5	/* Auto clear function select bit of transmit enable bit */
#define		sss_u2smr		u2smr_addr.bit.b6	/* Transmit start condition select bit */

/*------------------------------------------------------
	UART2 transmit/receive mode register
------------------------------------------------------*/
union byte_def u2mr_addr;
#define		u2mr			u2mr_addr.byte

#define		smd0_u2mr		u2mr_addr.bit.b0	/* Serial I/O mode select bit */
#define		smd1_u2mr		u2mr_addr.bit.b1	/* Serial I/O mode select bit */
#define		smd2_u2mr		u2mr_addr.bit.b2	/* Serial I/O mode select bit */
#define		ckdir_u2mr		u2mr_addr.bit.b3	/* Internal/external clock select bit */
#define		stps_u2mr		u2mr_addr.bit.b4	/* Stop bit length select bit */
#define		pry_u2mr		u2mr_addr.bit.b5	/* Odd/even parity select bit */
#define		prye_u2mr		u2mr_addr.bit.b6	/* Parity enable bit */
#define		iopol_u2mr		u2mr_addr.bit.b7	/* TxD RxD I/O polarity reverse bit */

/*------------------------------------------------------
	UART2 bit rate generator ; Use "MOV" instruction when writing to this register.
------------------------------------------------------*/
union byte_def u2brg_addr;
#define		u2brg			u2brg_addr.byte

/*------------------------------------------------------
	UART2 transmit/receive control register 0
------------------------------------------------------*/
union byte_def u2c0_addr;
#define		u2c0			u2c0_addr.byte

#define		clk0_u2c0		u2c0_addr.bit.b0	/* BRG count source select bit */
#define		clk1_u2c0		u2c0_addr.bit.b1	/* BRG count source select bit */
#define		crs_u2c0		u2c0_addr.bit.b2	/* CTS~/RTS~ function select bit */
#define		txept_u2c0		u2c0_addr.bit.b3	/* Transmit register empty flag */
#define		crd_u2c0		u2c0_addr.bit.b4	/* CTS~/RTS~ disable bit */
#define		nch_u2c0		u2c0_addr.bit.b5	/* Data output select bit */
#define		ckpol_u2c0		u2c0_addr.bit.b6	/* CLK polarity select bit */
#define		uform_u2c0		u2c0_addr.bit.b7	/* Transfer format select bit */

/*------------------------------------------------------
	UART2 transmit/receive control register 1			
------------------------------------------------------*/
union byte_def u2c1_addr;
#define		u2c1			u2c1_addr.byte

#define		te_u2c1			u2c1_addr.bit.b0	/* Transmit enable bit */
#define		ti_u2c1			u2c1_addr.bit.b1	/* Transmit buffer empty flag */
#define		re_u2c1			u2c1_addr.bit.b2	/* Receive enable bit */
#define		ri_u2c1			u2c1_addr.bit.b3	/* Receive complete flag */
#define		u2irs			u2c1_addr.bit.b4	/* UART2 transmit interrupt cause select bit */
#define		u2rrm			u2c1_addr.bit.b5	/* UART2 continuous receive mode enable bit */
#define		u2lch			u2c1_addr.bit.b6	/* Data logic select bit */
#define		u2ere			u2c1_addr.bit.b7	/* Error signal output enable bit */

/*------------------------------------------------------
	Count start flag
------------------------------------------------------*/
union byte_def tabsr_addr;
#define		tabsr			tabsr_addr.byte

#define		ta0s			tabsr_addr.bit.b0	/* Timer A0 count start flag */
#define		ta1s			tabsr_addr.bit.b1	/* Timer A1 count start flag */
#define		ta2s			tabsr_addr.bit.b2	/* Timer A2 count start flag */
#define		ta3s			tabsr_addr.bit.b3	/* Timer A3 count start flag */
#define		ta4s			tabsr_addr.bit.b4	/* Timer A4 count start flag */
#define		tb0s			tabsr_addr.bit.b5	/* Timer B0 count start flag */
#define		tb1s			tabsr_addr.bit.b6	/* Timer B1 count start flag */
#define		tb2s			tabsr_addr.bit.b7	/* Timer B2 count start flag */

/*------------------------------------------------------