sfr62p.h

renesas m16c DMA data access sample the whole project is tested in HEW,and works corectly.

#define		cm27			cm2_addr.bit.b7		/* Operation select bit(when an oscillation stop is detected) */

/*------------------------------------------------------
	Watchdog timer start register
------------------------------------------------------*/
union byte_def wdts_addr;
#define		wdts			wdts_addr.byte

/*------------------------------------------------------
	Watchdog timer control register
------------------------------------------------------*/
union byte_def wdc_addr;
#define		wdc				wdc_addr.byte

#define		wdc7			wdc_addr.bit.b7		/* Prescaler select bit */

/*------------------------------------------------------
	Chip select expansion control register
------------------------------------------------------*/
union byte_def cse_addr;
#define		cse				cse_addr.byte

#define		cse00w			cse_addr.bit.b0		/* CS0~ wait expansion bit */
#define		cse01w			cse_addr.bit.b1		/* CS0~ wait expansion bit */
#define		cse10w			cse_addr.bit.b2		/* CS1~ wait expansion bit */
#define		cse11w			cse_addr.bit.b3		/* CS1~ wait expansion bit */
#define		cse20w			cse_addr.bit.b4		/* CS2~ wait expansion bit */
#define		cse21w			cse_addr.bit.b5		/* CS2~ wait expansion bit */
#define		cse30w			cse_addr.bit.b6		/* CS3~ wait expansion bit */
#define		cse31w			cse_addr.bit.b7		/* CS3~ wait expansion bit */

/*------------------------------------------------------
	PLL control register 0
------------------------------------------------------*/
union byte_def plc0_addr;
#define		plc0			plc0_addr.byte

#define		plc00			plc0_addr.bit.b0	/* Programmable counter select bit */
#define		plc01			plc0_addr.bit.b1	/* Programmable counter select bit */
#define		plc02			plc0_addr.bit.b2	/* Programmable counter select bit */
#define		plc06			plc0_addr.bit.b6	/* External low-pass filter connecting bit */
#define		plc07			plc0_addr.bit.b7	/* Operation enable bit */

/*------------------------------------------------------
	Processor mode register 2
------------------------------------------------------*/
union byte_def pm2_addr;
#define		pm2				pm2_addr.byte

#define		pm20			pm2_addr.bit.b0		/* Specifying wait when accessing SFR at PLL operation */

/*------------------------------------------------------
	 DMA0 control register
------------------------------------------------------*/
union byte_def dm0con_addr;
#define		dm0con			dm0con_addr.byte

#define		dmbit_dm0con	dm0con_addr.bit.b0	/* Transfer unit bit select bit */
#define		dmasl_dm0con	dm0con_addr.bit.b1	/* Repeat transfer mode select bit */
#define		dmas_dm0con		dm0con_addr.bit.b2	/* DMA request bit */
#define		dmae_dm0con		dm0con_addr.bit.b3	/* DMA enable bit */
#define		dsd_dm0con		dm0con_addr.bit.b4	/* Source address direction select bit */
#define		dad_dm0con		dm0con_addr.bit.b5	/* Destination address direction select bit */

/*------------------------------------------------------
	 DMA1 control register
------------------------------------------------------*/
union byte_def	dm1con_addr;
#define		dm1con			dm1con_addr.byte

#define		dmbit_dm1con	dm1con_addr.bit.b0	/* Transfer unit bit select bit */
#define		dmasl_dm1con	dm1con_addr.bit.b1	/* Repeat transfer mode select bit */
#define		dmas_dm1con		dm1con_addr.bit.b2	/* DMA request bit */
#define		dmae_dm1con		dm1con_addr.bit.b3	/* DMA enable bit */
#define		dsd_dm1con		dm1con_addr.bit.b4	/* Source address direction select bit */
#define		dad_dm1con		dm1con_addr.bit.b5	/* Destination address direction select bit */

/*------------------------------------------------------
	INT3 interrupt control register
------------------------------------------------------*/
union byte_def int3ic_addr;
#define		int3ic			int3ic_addr.byte

#define		ilvl0_int3ic	int3ic_addr.bit.b0	/* Interrupt priority level select bit */
#define		ilvl1_int3ic	int3ic_addr.bit.b1	/* Interrupt priority level select bit */
#define		ilvl2_int3ic	int3ic_addr.bit.b2	/* Interrupt priority level select bit */
#define		ir_int3ic		int3ic_addr.bit.b3	/* Interrupt request bit */
#define		pol_int3ic		int3ic_addr.bit.b4	/* Polarity select bit */

/*------------------------------------------------------
	Timer B5 interrupt control register
------------------------------------------------------*/
union byte_def tb5ic_addr;
#define		tb5ic			tb5ic_addr.byte

#define		ilvl0_tb5ic		tb5ic_addr.bit.b0	/* Interrupt priority level select bit */
#define		ilvl1_tb5ic		tb5ic_addr.bit.b1	/* Interrupt priority level select bit */
#define		ilvl2_tb5ic		tb5ic_addr.bit.b2	/* Interrupt priority level select bit */
#define		ir_tb5ic		tb5ic_addr.bit.b3	/* Interrupt request bit */

/*------------------------------------------------------
	Timer B4 interrupt control register
------------------------------------------------------*/
union byte_def tb4ic_addr;
#define		tb4ic			tb4ic_addr.byte

#define		ilvl0_tb4ic		tb4ic_addr.bit.b0	/* Interrupt priority level select bit */
#define		ilvl1_tb4ic		tb4ic_addr.bit.b1	/* Interrupt priority level select bit */
#define		ilvl2_tb4ic		tb4ic_addr.bit.b2	/* Interrupt priority level select bit */
#define		ir_tb4ic		tb4ic_addr.bit.b3	/* Interrupt request bit */

/*------------------------------------------------------
	Timer B3 interrupt control register
------------------------------------------------------*/
union byte_def tb3ic_addr;
#define		tb3ic			tb3ic_addr.byte

#define		ilvl0_tb3ic		tb3ic_addr.bit.b0	/* Interrupt priority level select bit */
#define		ilvl1_tb3ic		tb3ic_addr.bit.b1	/* Interrupt priority level select bit */
#define		ilvl2_tb3ic		tb3ic_addr.bit.b2	/* Interrupt priority level select bit */
#define		ir_tb3ic		tb3ic_addr.bit.b3	/* Interrupt request bit */

/*------------------------------------------------------
	SI/O4 interrupt control register
------------------------------------------------------*/
union byte_def s4ic_addr;
#define		s4ic			s4ic_addr.byte

#define		ilvl0_s4ic		s4ic_addr.bit.b0	/* Interrupt priority level select bit */
#define		ilvl1_s4ic		s4ic_addr.bit.b1	/* Interrupt priority level select bit */
#define		ilvl2_s4ic		s4ic_addr.bit.b2	/* Interrupt priority level select bit */
#define		ir_s4ic			s4ic_addr.bit.b3	/* Interrupt request bit */
#define		pol_s4ic		s4ic_addr.bit.b4	/* Polarity select bit */

/*------------------------------------------------------
	SI/O3 interrupt control register
------------------------------------------------------*/
union byte_def s3ic_addr;
#define		s3ic			s3ic_addr.byte

#define		ilvl0_s3ic		s3ic_addr.bit.b0	/* Interrupt priority level select bit */
#define		ilvl1_s3ic		s3ic_addr.bit.b1	/* Interrupt priority level select bit */
#define		ilvl2_s3ic		s3ic_addr.bit.b2	/* Interrupt priority level select bit */
#define		ir_s3ic			s3ic_addr.bit.b3	/* Interrupt request bit */
#define		pol_s3ic		s3ic_addr.bit.b4	/* Polarity select bit */

/*------------------------------------------------------
	INT5 interrupt control register
------------------------------------------------------*/
union byte_def int5ic_addr;
#define		int5ic			int5ic_addr.byte

#define		ilvl0_int5ic	int5ic_addr.bit.b0	/* Interrupt priority level select bit */
#define		ilvl1_int5ic	int5ic_addr.bit.b1	/* Interrupt priority level select bit */
#define		ilvl2_int5ic	int5ic_addr.bit.b2	/* Interrupt priority level select bit */
#define		ir_int5ic		int5ic_addr.bit.b3	/* Interrupt request bit */
#define		pol_int5ic		int5ic_addr.bit.b4	/* Polarity select bit */

/*------------------------------------------------------
	INT4 interrupt control register
------------------------------------------------------*/
union byte_def int4ic_addr;
#define		int4ic			int4ic_addr.byte

#define		ilvl0_int4ic	int4ic_addr.bit.b0	/* Interrupt priority level select bit */
#define		ilvl1_int4ic	int4ic_addr.bit.b1	/* Interrupt priority level select bit */
#define		ilvl2_int4ic	int4ic_addr.bit.b2	/* Interrupt priority level select bit */
#define		ir_int4ic		int4ic_addr.bit.b3	/* Interrupt request bit */
#define		pol_int4ic		int4ic_addr.bit.b4	/* Polarity select bit */

/*------------------------------------------------------
	Bus collision detection interrupt control register
------------------------------------------------------*/
union byte_def bcnic_addr;
#define		bcnic			bcnic_addr.byte

#define		ilvl0_bcnic		bcnic_addr.bit.b0	/* Interrupt priority level select bit */
#define		ilvl1_bcnic		bcnic_addr.bit.b1	/* Interrupt priority level select bit */
#define		ilvl2_bcnic		bcnic_addr.bit.b2	/* Interrupt priority level select bit */
#define		ir_bcnic		bcnic_addr.bit.b3	/* Interrupt request bit */

/*------------------------------------------------------
	DMA0 interrupt control register
------------------------------------------------------*/
union byte_def dm0ic_addr;
#define		dm0ic			dm0ic_addr.byte

#define		ilvl0_dm0ic		dm0ic_addr.bit.b0	/* Interrupt priority level select bit */
#define		ilvl1_dm0ic		dm0ic_addr.bit.b1	/* Interrupt priority level select bit */
#define		ilvl2_dm0ic		dm0ic_addr.bit.b2	/* Interrupt priority level select bit */
#define		ir_dm0ic		dm0ic_addr.bit.b3	/* Interrupt request bit */

/*------------------------------------------------------
	DMA1 interrupt control register
------------------------------------------------------*/
union byte_def dm1ic_addr;
#define		dm1ic			dm1ic_addr.byte

#define		ilvl0_dm1ic		dm1ic_addr.bit.b0	/* Interrupt priority level select bit */
#define		ilvl1_dm1ic		dm1ic_addr.bit.b1	/* Interrupt priority level select bit */
#define		ilvl2_dm1ic		dm1ic_addr.bit.b2	/* Interrupt priority level select bit */
#define		ir_dm1ic		dm1ic_addr.bit.b3	/* Interrupt request bit */

/*------------------------------------------------------
	Key input interrupt control register
------------------------------------------------------*/
union byte_def kupic_addr;
#define		kupic			kupic_addr.byte

#define		ilvl0_kupic		kupic_addr.bit.b0	/* Interrupt priority level select bit */
#define		ilvl1_kupic		kupic_addr.bit.b1	/* Interrupt priority level select bit */
#define		ilvl2_kupic		kupic_addr.bit.b2	/* Interrupt priority level select bit */
#define		ir_kupic		kupic_addr.bit.b3	/* Interrupt request bit */

/*------------------------------------------------------
	A-D conversion interrupt control register
------------------------------------------------------*/
union byte_def adic_addr;
#define		adic			adic_addr.byte

#define		ilvl0_adic		adic_addr.bit.b0	/* Interrupt priority level select bit */
#define		ilvl1_adic		adic_addr.bit.b1	/* Interrupt priority level select bit */
#define		ilvl2_adic		adic_addr.bit.b2	/* Interrupt priority level select bit */
#define		ir_adic			adic_addr.bit.b3	/* Interrupt request bit */

/*------------------------------------------------------
	UART2 transmit interrupt control register
------------------------------------------------------*/
union byte_def s2tic_addr;
#define		s2tic			s2tic_addr.byte

#define		ilvl0_s2tic		s2tic_addr.bit.b0	/* Interrupt priority level select bit */
#define		ilvl1_s2tic		s2tic_addr.bit.b1	/* Interrupt priority level select bit */
#define		ilvl2_s2tic		s2tic_addr.bit.b2	/* Interrupt priority level select bit */
#define		ir_s2tic		s2tic_addr.bit.b3	/* Interrupt request bit */

/*------------------------------------------------------
	UART2 receive interrupt control register
------------------------------------------------------*/
union byte_def s2ric_addr;
#define		s2ric			s2ric_addr.byte

#define		ilvl0_s2ric		s2ric_addr.bit.b0	/* Interrupt priority level select bit */
#define		ilvl1_s2ric		s2ric_addr.bit.b1	/* Interrupt priority level select bit */
#define		ilvl2_s2ric		s2ric_addr.bit.b2	/* Interrupt priority level select bit */
#define		ir_s2ric		s2ric_addr.bit.b3	/* Interrupt request bit */

/*------------------------------------------------------
	UART0 transmit interrupt control register
------------------------------------------------------*/
union byte_def s0tic_addr;
#define		s0tic			s0tic_addr.byte

#define		ilvl0_s0tic		s0tic_addr.bit.b0	/* Interrupt priority level select bit */
#define		ilvl1_s0tic		s0tic_addr.bit.b1	/* Interrupt priority level select bit */
#define		ilvl2_s0tic		s0tic_addr.bit.b2	/* Interrupt priority level select bit */
#define		ir_s0tic		s0tic_addr.bit.b3	/* Interrupt request bit */

/*------------------------------------------------------
	UART0 receive interrupt control register
------------------------------------------------------*/
union byte_def s0ric_addr;
#define		s0ric			s0ric_addr.byte

#define		ilvl0_s0ric		s0ric_addr.bit.b0	/* Interrupt priority level select bit */
#define		ilvl1_s0ric		s0ric_addr.bit.b1	/* Interrupt priority level select bit */
#define		ilvl2_s0ric		s0ric_addr.bit.b2	/* Interrupt priority level select bit */
#define		ir_s0ric		s0ric_addr.bit.b3	/* Interrupt request bit */

/*------------------------------------------------------
	UART1 transmit interrupt control register
------------------------------------------------------*/
union byte_def s1tic_addr;
#define		s1tic			s1tic_addr.byte

#define		ilvl0_s1tic		s1tic_addr.bit.b0	/* Interrupt priority level select bit */
#define		ilvl1_s1tic		s1tic_addr.bit.b1	/* Interrupt priority level select bit */
#define		ilvl2_s1tic		s1tic_addr.bit.b2	/* Interrupt priority level select bit */
#define		ir_s1tic		s1tic_addr.bit.b3	/* Interrupt request bit */

/*------------------------------------------------------
	UART1 receive interrupt control register
------------------------------------------------------*/
union byte_def s1ric_addr;
#define		s1ric			s1ric_addr.byte

#define		ilvl0_s1ric		s1ric_addr.bit.b0	/* Interrupt priority level select bit */
#define		ilvl1_s1ric		s1ric_addr.bit.b1	/* Interrupt priority level select bit */
#define		ilvl2_s1ric		s1ric_addr.bit.b2	/* Interrupt priority level select bit */
#define		ir_s1ric		s1ric_addr.bit.b3	/* Interrupt request bit */

/*------------------------------------------------------
	Timer A0 receive interrupt control register
------------------------------------------------------*/
union byte_def ta0ic_addr;
#define		ta0ic			ta0ic_addr.byte