📄 video_test.c
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/*****************************************************************
Copyright (C), 2004-2008, Wintech Digital System Co., Ltd.
FileName: video_test.c
Description: Video Loopback Test
******************************************************************/
#include "davincievm_i2c.h"
#include "davincievm_vpss.h"
#include "csl_ccdc.h"
#include "csl_resz.h"
#include "csl_ccdc_pal.h"
#include "csl_resz_pal2cif.h"
#define TVP5146_I2C_ADDR 0x5D
#define IMG_WIDTH 704
#define IMG_HEIGTH 576
/* ------------------------------------------------------------------------ *
* *
* tvp5146_rset *
* *
* Set codec register regnum to value regval *
* *
* ------------------------------------------------------------------------ */
void tvp5146_rset( Uint8 regnum, Uint8 regval )
{
Uint8 cmd[2];
cmd[0] = regnum; // 8-bit Register Address
cmd[1] = regval; // 8-bit Register Data
DAVINCIEVM_I2C_write( TVP5146_I2C_ADDR, cmd, 2, 1 );
}
/* ------------------------------------------------------------------------ *
* *
* tvp5146_rget *
* *
* Return value of codec register regnum *
* *
* ------------------------------------------------------------------------ */
Uint8 tvp5146_rget( Uint8 regnum )
{
Uint8 cmd[2];
cmd[0] = regnum; // 8-bit Register Address
cmd[1] = 0; // 8-bit Register Data
DAVINCIEVM_I2C_write( TVP5146_I2C_ADDR, cmd, 1, 0 );
DAVINCIEVM_I2C_read ( TVP5146_I2C_ADDR, cmd, 1, 1 );
return cmd[0];
}
/* ------------------------------------------------------------------------ *
* *
* tvp5146_init( ) *
* *
* Initialize the TVP5146 *
* *
* ------------------------------------------------------------------------ */
void tvp5146_init( )
{
DAVINCIEVM_waitusec( 1000 ); // wait 1 msec
tvp5146_rset( 0xE8, 0x02 ); // Initalize TVP5146, must do after power on
tvp5146_rset( 0xE9, 0x00 );
tvp5146_rset( 0xEA, 0x80 );
tvp5146_rset( 0xE0, 0x01 );
tvp5146_rset( 0xE8, 0x60 );
tvp5146_rset( 0xE9, 0x00 );
tvp5146_rset( 0xEA, 0xB0 );
tvp5146_rset( 0xE0, 0x01 );
tvp5146_rset( 0xE0, 0x00 );
DAVINCIEVM_waitusec( 1000 ); // wait 1 msec
#ifdef Svideo
tvp5146_rset( 0x00, 0x46 ); // Input Video: S-video: VI_2_C(Y) VI_1_C(C)
#else
tvp5146_rset( 0x00, 0x05 ); // Input Video: CVBS : VI_2_B
#endif
tvp5146_rset( 0x02, 0x00 ); // PAL
//tvp5146_rset( 0x02, 0x01 ); // NTSC
tvp5146_rset( 0x16, 0x58 ); // AVID Start Pixel
tvp5146_rset( 0x17, 0x00 ); // NTSC:55h PAL:58h
tvp5146_rset( 0x18, 0x28 ); // AVID Stop Pixel
tvp5146_rset( 0x19, 0x03 ); // NTSC:325h PAL:328h
tvp5146_rset( 0x1A, 0x00 ); // HSYNC Start Pixel
tvp5146_rset( 0x1B, 0x00 );
tvp5146_rset( 0x1C, 0x80 ); // HSYNC Stop Pixel
tvp5146_rset( 0x1D, 0x00 );
tvp5146_rset( 0x1E, 0x01 ); // VSYNC Start Line
tvp5146_rset( 0x1F, 0x00 ); // NTSC: default 004h, PAL: default 001h
tvp5146_rset( 0x20, 0x04 ); // VSYNC Stop Line
tvp5146_rset( 0x21, 0x00 ); // NTSC: default 007h, PAL: default 004h
tvp5146_rset( 0x22, 0x6f ); // VBLK Start Line
tvp5146_rset( 0x23, 0x02 ); // NTSC: default 001h, PAL: default 623 (26Fh)
tvp5146_rset( 0x24, 0x17 ); // VBLK Stop Line
tvp5146_rset( 0x25, 0x00 ); // NTSC: default 21 (15h), PAL: default 23 (17h)
tvp5146_rset( 0x34, 0x11 ); // Enabling clock & Y/CB/CR input format
DAVINCIEVM_waitusec( 1000 ); // wait 1 msec
}
#define PAL 1
#if NTSC
#define BASEP_X 0x7A // 122
#define BASEP_Y 0x12 // 18
#elif PAL
#define BASEP_X 0x84 // 132
#define BASEP_Y 0x16 // 22
#endif
/* ------------------------------------------------------------------------ *
* *
* vpfe_init( ) *
* *
* PAL: *
* Width: 720 *
* Height: 576 *
* *
* *
* ------------------------------------------------------------------------ */
void vpfe_init( Uint32 buffer, Uint32 width, Uint32 height )
{
CSL_CcdcHandle hCcdc;
CSL_CcdcObj ccdcObj;
CSL_Status status;
CSL_CcdcHwSetup hwSetup = CSL_CCDC_HWSETUP_PAL;
Uint32 sdramoff, ccdcen, sdramouten;
CSL_CcdcSdrOutSizeConfig outsize = {
0,
720 << 1,
0,
0,
576 >> 1
};
CSL_CcdcPixLinesConfig pixlines = {
720,
625
};
ccdcen = CSL_CCDC_ENABLE;
sdramouten = CSL_CCDC_SDRAM_OUT_ENABLE;
sdramoff = width << 1;
hCcdc = CSL_ccdcOpen(&ccdcObj,
CSL_CCDC_0,
CSL_EXCLUSIVE,
&status);
CSL_ccdcHwSetup(hCcdc, &hwSetup);
status = CSL_ccdcHwControl(hCcdc,
CSL_CCDC_CMD_SDRAM_OUTPUT_ENABLE,
&sdramouten);
status = CSL_ccdcHwControl(hCcdc,
CSL_CCDC_CMD_SET_PIX_LINES,
&pixlines);
status = CSL_ccdcHwControl(hCcdc,
CSL_CCDC_CMD_SET_SDRAM_OUT_SIZE,
&outsize);
status = CSL_ccdcHwControl(hCcdc,
CSL_CCDC_CMD_SET_SDRAM_OFFSET,
&sdramoff);
status = CSL_ccdcHwControl(hCcdc,
CSL_CCDC_CMD_SET_SDRAM_ADDR,
(void *)buffer);
//CCDC_FMTCFG = 0x00036000;
//SDR_REQ_EXP_1 = 0x000ff000;
status = CSL_ccdcHwControl(hCcdc,
CSL_CCDC_CMD_ENABLE,
&ccdcen);
}
void Resize_init( Uint32 buffer )
{
CSL_ReszHandle hResz;
CSL_ReszObj reszObj;
CSL_ReszHwSetup hwSetup;
CSL_Status status;
Uint32 command;
hResz = CSL_reszOpen(&reszObj,
CSL_RESZ_0,
CSL_EXCLUSIVE,
&status);
hwSetup = CSL_RESZ_HWSETUP_DEFAULTS;
/*status = CSL_reszHwControl(hResz,
CSL_RESZ_CMD_CALCULATE_HW_SETUP,
&hwSetup);*/
CSL_reszHwSetup(hResz, &hwSetup);
/* command = CSL_RESZ_ENABLE;
status = CSL_reszHwControl(hResz,
CSL_RESZ_CMD_ENABLE,
&command);*/
}
/* ------------------------------------------------------------------------ *
* *
* vpbe_init( ) *
* *
* PAL: *
* Width: 720 *
* Height: 576 *
* *
* *
* ------------------------------------------------------------------------ */
void vpbe_init( Uint32 buffer, Uint32 width, Uint32 height, Uint32 cb_enable )
{
/*
* Setup VPBE
*/
VPSS_CLK_CTRL = 0x00000018; // Enable DAC and VENC clock, both at 27 MHz
VPBE_PCR = 0; // No clock div, clock enable
/*
* Setup OSD
*/
OSD_MODE = 0x000000fc; // Blackground color blue using clut in ROM0
OSD_OSDWIN0MD = 0; // Disable both osd windows and cursor window
OSD_OSDWIN1MD = 0;
OSD_RECTCUR = 0;
OSD_VIDWIN0OFST = width >> 4;
OSD_VIDWIN0ADR = buffer;
OSD_BASEPX = BASEP_X;
OSD_BASEPY = BASEP_Y;
OSD_VIDWIN0XP = 0;
OSD_VIDWIN0YP = 0;
OSD_VIDWIN0XL = width;
OSD_VIDWIN0YL = height >> 1;
OSD_MISCCTL = 0;
OSD_VIDWINMD = 0x00000003; // Disable vwindow 1 and enable vwindow 0
// Frame mode with no up-scaling
/*
* Setup VENC
*/
VENC_VMOD = 0x00000043; // Standard PAL interlaced output
VENC_VDPRO = cb_enable << 8;
#ifdef Svideo
VENC_DACSEL = 0x00004210;
#else
VENC_CMPNT = 0x00008700;
VENC_DACSEL = 0x00005430;
#endif
VENC_DACTST = 0;
}
/* ------------------------------------------------------------------------ *
* *
* video_loopback_test( ) *
* *
* *
* *
* ------------------------------------------------------------------------ */
Int16 video_loopback_test( )
{
//Uint16 vpfe_mem[414720];
//vpfe_mem = (Uint8 *)malloc(IMG_WIDTH * IMG_HEIGTH);
tvp5146_init( );
#ifdef SDRAM
Resize_init(0x81000000);
vpfe_init( 0x81800000, 720, 576 ); // Setup Front-End
vpbe_init( 0x82000000, 352, 286, 0 ); // Setup Back-End
while(1)
{
if ((RESIZER_PCR == 0) && ((AINTC_IRQ0 & 0x1)==0))
{
RESIZER_PCR = 0x1;
AINTC_IRQ0 |= 0x1;
}
}
#else
Resize_init(0x81000000);
vpfe_init( 0x81800000, 720, 576 ); // Setup Front-End
vpbe_init( 0x82000000, 720, 573, 0 ); // Setup Back-End
while(1)
{
if (RESIZER_PCR == 0)
RESIZER_PCR = 0x1;
}
#endif
//vpfe_init( 0x82000000, 720, 576 ); // Setup Front-End
//vpbe_init( 0x82000000, 720, 576, 0 ); // Setup Back-End
return 0;
}
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