multi.txt

四则运算的模拟

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity multi is
	port (
		A: in STD_LOGIC_VECTOR (3 downto 0);
		B: in STD_LOGIC_VECTOR (3 downto 0);
		C: out STD_LOGIC_VECTOR (6 downto 0)
	);
end multi;



architecture multi_arch of multi is
signal temp1 : STD_LOGIC_VECTOR (5 downto 0);
signal temp2 : STD_LOGIC_VECTOR (5 downto 0);
signal temp3 : STD_LOGIC_VECTOR (5 downto 0);

signal add1 : STD_LOGIC_VECTOR (5 downto 0);
signal add2 : STD_LOGIC_VECTOR (5 downto 0);
signal add3 : STD_LOGIC_VECTOR (5 downto 0);
signal add  : STD_LOGIC_VECTOR (5 downto 0);
signal answer : STD_LOGIC_VECTOR (6 downto 0);
signal zero : STD_LOGIC_VECTOR (5 downto 0);
SIGNAL COUT1, COUT2, COUT3 :STD_LOGIC;
begin


zero(0) <= '0';
zero(1) <= '0';
zero(2) <= '0';
zero(3) <= '0';
zero(4) <= '0';
zero(5) <= '0';

temp1(0) <= A(0);
temp1(1) <= A(1);
temp1(2) <= A(2);
temp1(3) <= '0';
temp1(4) <= '0';
temp1(5) <= '0';

temp2(0) <= '0';
temp2(1) <= A(0);
temp2(2) <= A(1);
temp2(3) <= A(2);
temp2(4) <= '0';
temp2(5) <= '0';

temp3(0) <= '0';
temp3(1) <= '0';
temp3(2) <= A(0);
temp3(3) <= A(1);
temp3(4) <= A(2);
temp3(5) <= '0';

add1 <= zero when B(0) = '0' else temp1;
add2 <= zero when B(1) = '0' else temp2;
add3 <= zero when B(2) = '0' else temp3;
add <= add1 + add2;
C(5 downto 0)<= add + add3;
C(6) <= A(3) xor B(3);
end multi_arch;