div.txt

四则运算的模拟

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity div is
	port (
		DIVz: out STD_LOGIC;
		A: in STD_LOGIC_VECTOR (3 downto 0);
		B: in STD_LOGIC_VECTOR (3 downto 0);
		C: out STD_LOGIC_VECTOR (3 downto 0)
	);
end div;

architecture div_arch of div is
signal remainS0 : STD_LOGIC_VECTOR (5 downto 0);
signal remainS1 : STD_LOGIC_VECTOR (5 downto 0);
signal remainS2 : STD_LOGIC_VECTOR (5 downto 0);
signal remainS3 : STD_LOGIC_VECTOR (5 downto 0);

signal diverS0 : STD_LOGIC_VECTOR (5 downto 0);
signal diverS1 : STD_LOGIC_VECTOR (5 downto 0);
signal diverS2 : STD_LOGIC_VECTOR (5 downto 0);
signal diverS3 : STD_LOGIC_VECTOR (5 downto 0);

signal Q_TEMP : STD_LOGIC_VECTOR (3 downto 0);


begin

	diverS0 <=Z0 & B(2 downto 0);
	remainS3  <=Z1& A(2 downto 0);
	diverS1 <= diverS0(4 downto 0) & '0';
	diverS2 <= diverS1(4 downto 0) & '0';
	diverS3 <= diverS2(4 downto 0) & '0';
	remainS2 <= remainS3 - diverS2 when Q_TEMP(2) = '1' else remainS3;
	remainS1 <= remainS2 - diverS1 when Q_TEMP(1) = '1' else remainS2;
	remainS0 <= remainS1 - diverS0 when Q_TEMP(0) = '1' else remainS1;
	Q_TEMP(2) <= '1' when (remainS3 >= diverS2) else '0';
	Q_TEMP(1) <= '1' when (remainS2 >= diverS1) else '0';
	Q_TEMP(0) <= '1' when (remainS1 >= diverS0) else '0';
	Q_TEMP(3) <= A(3) xor B(3);
	C <=Q_TEMP;
end div_arch;