ad.vhd.bak

输入为八位十进制数

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity ad is
	PORT(
		clk                            : in      std_logic;
		data_ad                        : in      std_logic_vector(7 downto 0);
		douta,doutb,doutc,doutd        : out     std_logic_vector(4 downto 0)
		);
end;

ARCHITECTURE behave of ad is

	TYPE STATE_TYPE IS (s0,s1,s2,s3);
	signal state: STATE_TYPE;

    signal a,b,c,d              : std_logic_vector(9 downto 0);
    signal dis_a;dis_b          : std_logic_vector(4 downto 0);
    signal dis_c;dis_d          : std_logic_vector(4 downto 0);
    signal data_transf_buff     : std_logic_vector(10 downto 0);
    
begin

-------------------------------------

process (clk,state)
	begin
	  if clk 'event and clk ='1' then
	    case state is
			
		when s0 =>
		    a(7 downto 0)<=data_ad;
            state<=s1;
        when s1 =>
		    b(7 downto 0)<=data_ad;		
            state<=s2;
		when s2 =>
            c(7 downto 0)<=data_ad;
            state<=s3;       
        when s3 =>
            d<= data_ad + a + b + c;
            data_transf_buff(10 downto 1)<=d;
            state<=s4;
-----------------------------------------------------------------
                when s4 =>				    
				    dis_a <= "00000"; dis_b <= "00000";
				    dis_c <= "00000"; dis_d <= "00000"; 
                    state<=s5;

				when s5 =>
				    if data_transf_buff >= "00111110100" then
				          data_transf_buff <= data_transf_buff - "00111110100";    
				          dis_a <= dis_a + 1;
				          state<=s6;
				    else  
				          state<=s5; 
				    end if;
				
				when s6 =>
				    if data_transf_buff >= "00001100100" then
				          data_transf_buff <= data_transf_buff - "00001100100";    
				          dis_b <= dis_b + 1;
				          state<=s6;
				    else  
				          state<=s7; 
				    end if;
				
				when s7 =>
				    if data_transf_buff >= "00000001010" then
				          data_transf_buff <= data_transf_buff - "00000001010";    
				          dis_c <= dis_c + 1;
				          state<=s7;
				    else  
				          dis_d <= data_transf_buff(4 downto 0);
				          state<=s8; 
				    end if;
				when s8 =>
				    douta <= dis_a;doutb <= dis_b;
				    doutc <= dis_c;doutd <= dis_d;
                    state <= s0;
            
	     end case;
	  end if;
end process;

end behave;