comp.fit.qmsg

输入为八位十进制数

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.749 ns register register " "Info: Estimated most critical path is register to register delay of 5.749 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns frequence:inst\|t_2\[3\] 1 REG LAB_X21_Y7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X21_Y7; Fanout = 2; REG Node = 'frequence:inst\|t_2\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { frequence:inst|t_2[3] } "NODE_NAME" } } { "frequence.vhd" "" { Text "D:/altera/comp/frequence.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.580 ns) + CELL(0.442 ns) 1.022 ns frequence:inst\|Equal3~35 2 COMB LAB_X20_Y7 1 " "Info: 2: + IC(0.580 ns) + CELL(0.442 ns) = 1.022 ns; Loc. = LAB_X20_Y7; Fanout = 1; COMB Node = 'frequence:inst\|Equal3~35'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.022 ns" { frequence:inst|t_2[3] frequence:inst|Equal3~35 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.265 ns) + CELL(0.442 ns) 1.729 ns frequence:inst\|Equal3~36 3 COMB LAB_X20_Y7 2 " "Info: 3: + IC(0.265 ns) + CELL(0.442 ns) = 1.729 ns; Loc. = LAB_X20_Y7; Fanout = 2; COMB Node = 'frequence:inst\|Equal3~36'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.707 ns" { frequence:inst|Equal3~35 frequence:inst|Equal3~36 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.292 ns) 2.383 ns display:inst1\|LED\[3\]~777 4 COMB LAB_X20_Y7 5 " "Info: 4: + IC(0.362 ns) + CELL(0.292 ns) = 2.383 ns; Loc. = LAB_X20_Y7; Fanout = 5; COMB Node = 'display:inst1\|LED\[3\]~777'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.654 ns" { frequence:inst|Equal3~36 display:inst1|LED[3]~777 } "NODE_NAME" } } { "display.vhd" "" { Text "D:/altera/comp/display.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.832 ns) + CELL(0.114 ns) 3.329 ns display:inst1\|Mux1~81 5 COMB LAB_X21_Y7 1 " "Info: 5: + IC(0.832 ns) + CELL(0.114 ns) = 3.329 ns; Loc. = LAB_X21_Y7; Fanout = 1; COMB Node = 'display:inst1\|Mux1~81'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.946 ns" { display:inst1|LED[3]~777 display:inst1|Mux1~81 } "NODE_NAME" } } { "display.vhd" "" { Text "D:/altera/comp/display.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.832 ns) + CELL(0.114 ns) 4.275 ns display:inst1\|Mux1~82 6 COMB LAB_X20_Y7 1 " "Info: 6: + IC(0.832 ns) + CELL(0.114 ns) = 4.275 ns; Loc. = LAB_X20_Y7; Fanout = 1; COMB Node = 'display:inst1\|Mux1~82'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.946 ns" { display:inst1|Mux1~81 display:inst1|Mux1~82 } "NODE_NAME" } } { "display.vhd" "" { Text "D:/altera/comp/display.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.736 ns) + CELL(0.738 ns) 5.749 ns display:inst1\|LED\[3\] 7 REG LAB_X22_Y7 8 " "Info: 7: + IC(0.736 ns) + CELL(0.738 ns) = 5.749 ns; Loc. = LAB_X22_Y7; Fanout = 8; REG Node = 'display:inst1\|LED\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.474 ns" { display:inst1|Mux1~82 display:inst1|LED[3] } "NODE_NAME" } } { "display.vhd" "" { Text "D:/altera/comp/display.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.142 ns ( 37.26 % ) " "Info: Total cell delay = 2.142 ns ( 37.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.607 ns ( 62.74 % ) " "Info: Total interconnect delay = 3.607 ns ( 62.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.749 ns" { frequence:inst|t_2[3] frequence:inst|Equal3~35 frequence:inst|Equal3~36 display:inst1|LED[3]~777 display:inst1|Mux1~81 display:inst1|Mux1~82 display:inst1|LED[3] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Warning" "WFITAPI_FITAPI_WARNING_VPR_VERY_HIGH_HOLD_REQUIREMENTS_DETECTED" "7 942 " "Warning: 7 (of 942) connections in the design require a large routing delay to achieve hold requirements. Please check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks." { { "Info" "IFITAPI_FITAPI_INFO_VPR_REGISTERS_WITH_VERY_HIGH_HOLD_REQUIREMENTS" "7 " "Info: Found 7 Registers with very high hold time requirements" { { "Info" "IFITAPI_FITAPI_ATOM_NAME" "display:inst1\|scale\[5\] " "Info: Node \"display:inst1\|scale\[5\]\"" {  } { { "display.vhd" "" { Text "D:/altera/comp/display.vhd" 41 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "display:inst1\|scale\[5\]" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { display:inst1|scale[5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { display:inst1|scale[5] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "display:inst1\|LED\[4\] " "Info: Node \"display:inst1\|LED\[4\]\"" {  } { { "display.vhd" "" { Text "D:/altera/comp/display.vhd" 41 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "display:inst1\|LED\[4\]" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { display:inst1|LED[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { display:inst1|LED[4] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME_DUAL_OUTPUT" "display:inst1\|scale\[4\] " "Info: Node \"display:inst1\|scale\[4\]\" (dual-output)" { { "Info" "IFITAPI_FITAPI_ATOM_REGISTERED_OUTPUT" "display:inst1\|scale\[4\] " "Info: Registered output is \"display:inst1\|scale\[4\]\"" {  } { { "display.vhd" "" { Text "D:/altera/comp/display.vhd" 41 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "display:inst1\|scale\[4\]" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { display:inst1|scale[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { display:inst1|scale[4] } "NODE_NAME" } }  } 0 0 "Registered output is \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_COMBINATORIAL_OUTPUT" "display:inst1\|LED\[3\]~776 " "Info: Combinational output is \"display:inst1\|LED\[3\]~776\"" {  } { { "display.vhd" "" { Text "D:/altera/comp/display.vhd" 41 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "display:inst1\|scale\[4\]" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { display:inst1|scale[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { display:inst1|scale[4] } "NODE_NAME" } }  } 0 0 "Combinational output is \"%1!s!\"" 0 0 "" 0}  } { { "display.vhd" "" { Text "D:/altera/comp/display.vhd" 41 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "display:inst1\|scale\[4\]" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { display:inst1|scale[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { display:inst1|scale[4] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\" (dual-output)" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "display:inst1\|LED\[1\] " "Info: Node \"display:inst1\|LED\[1\]\"" {  } { { "display.vhd" "" { Text "D:/altera/comp/display.vhd" 41 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "display:inst1\|LED\[1\]" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { display:inst1|LED[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { display:inst1|LED[1] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "ad:inst2\|doutd\[1\] " "Info: Node \"ad:inst2\|doutd\[1\]\"" {  } { { "ad.vhd" "" { Text "D:/altera/comp/ad.vhd" 29 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "ad:inst2\|doutd\[1\]" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ad:inst2|doutd[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ad:inst2|doutd[1] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "ad:inst2\|douta\[3\] " "Info: Node \"ad:inst2\|douta\[3\]\"" {  } { { "ad.vhd" "" { Text "D:/altera/comp/ad.vhd" 29 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "ad:inst2\|douta\[3\]" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ad:inst2|douta[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ad:inst2|douta[3] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "ad:inst2\|dis_a\[1\] " "Info: Node \"ad:inst2\|dis_a\[1\]\"" {  } { { "ad.vhd" "" { Text "D:/altera/comp/ad.vhd" 29 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "ad:inst2\|dis_a\[1\]" } } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ad:inst2|dis_a[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ad:inst2|dis_a[1] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Found %1!d! Registers with very high hold time requirements" 0 0 "" 0}  } {  } 0 0 "%1!d! (of %2!d!) connections in the design require a large routing delay to achieve hold requirements. Please check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks." 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "3 " "Info: Average interconnect usage is 3% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "5 X14_Y0 X27_Y14 " "Info: Peak interconnect usage is 5% of the available device resources in the region that extends from location X14_Y0 to location X27_Y14" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/altera/comp/comp.fit.smsg " "Info: Generated suppressed messages file D:/altera/comp/comp.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "171 " "Info: Allocated 171 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 04 14:08:51 2008 " "Info: Processing ended: Sun May 04 14:08:51 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}