📄 frequence.vhd
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity frequence is
port(
fin : in std_logic;
clk_1Hz : in std_logic;
douta : out std_logic_vector(4 downto 0);
doutb : out std_logic_vector(4 downto 0);
doutc : out std_logic_vector(4 downto 0);
doutd : out std_logic_vector(4 downto 0)
);
end;
architecture behav of frequence is
signal clk_half : std_logic;
signal r_1,r_2,r_3,r_4,r_5 : std_logic_vector(4 downto 0);
signal t_1,t_2,t_3,t_4,t_5 : std_logic_vector(4 downto 0);
begin
process(clk_1Hz)
begin
if rising_edge(clk_1Hz) then
clk_half<=NOT clk_half;
end if;
end process;
process(fin,clk_half)
begin
if rising_edge(fin) then
if clk_half='1' then r_1<=r_1+1;
if r_1>"01001" then r_1<="00000"; r_2<=r_2+1; end if;
if r_2>"01001" then r_2<="00000"; r_3<=r_3+1; end if;
if r_3>"01001" then r_3<="00000"; r_4<=r_4+1; end if;
if r_4>"01001" then r_4<="00000"; r_5<=r_5+1; end if;
if r_5>"01001" then r_1<="01001"; r_2<="01001"; r_3<="01001";
r_4<="01001"; r_5<="01001"; end if;
elsif clk_half='0' then
r_1<="00000";r_2<="00000";r_3<="00000";r_4<="00000";r_5<="00000";
end if;
end if;
end process;
process(clk_half)
begin
if falling_edge(clk_half) then
t_1<=r_1; t_3<=r_3; t_5<=r_5;
t_2<=r_2; t_4<=r_4;
end if;
end process;
-------------------------------------------------------------------------------------------
process(t_1,t_2,t_3,t_4,t_5)
begin
if t_5="00000" then
if t_4="00000" then douta<="11111";
else douta<=t_4; end if;
if t_3="00000" then doutb<="11111";
else doutb<=t_3; end if;
if t_2="00000" then doutc<="11111";
else doutc<=t_2; end if;
doutd<=t_1;
else doutd<=t_2;doutc<=t_3;
doutb<=t_4+"10000";
douta<=t_5;
end if;
end process;
end;
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