comp.qsf

输入为八位十进制数

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		comp_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C3T100C8
set_global_assignment -name TOP_LEVEL_ENTITY comp
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:51:39  APRIL 30, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 7.2
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name VHDL_FILE frequence.vhd
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name VHDL_FILE display.vhd
set_global_assignment -name BDF_FILE comp.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE comp.vwf
set_location_assignment PIN_10 -to clk
set_location_assignment PIN_21 -to fin
set_location_assignment PIN_86 -to dout[0]
set_location_assignment PIN_84 -to dout[1]
set_location_assignment PIN_76 -to dout[2]
set_location_assignment PIN_78 -to dout[3]
set_location_assignment PIN_85 -to dout[4]
set_location_assignment PIN_87 -to dout[5]
set_location_assignment PIN_77 -to dout[6]
set_location_assignment PIN_79 -to dout[7]
set_location_assignment PIN_74 -to scale[7]
set_location_assignment PIN_71 -to scale[0]
set_location_assignment PIN_70 -to scale[1]
set_location_assignment PIN_69 -to scale[2]
set_location_assignment PIN_68 -to scale[3]
set_location_assignment PIN_72 -to scale[4]
set_location_assignment PIN_73 -to scale[5]
set_location_assignment PIN_75 -to scale[6]
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_location_assignment PIN_100 -to clk_1Hz
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name VHDL_FILE ad.vhd
set_location_assignment PIN_99 -to clk12M
set_location_assignment PIN_23 -to ad[0]
set_location_assignment PIN_25 -to ad[1]
set_location_assignment PIN_24 -to ad[2]
set_location_assignment PIN_38 -to ad[3]
set_location_assignment PIN_36 -to ad[4]
set_location_assignment PIN_34 -to ad[5]
set_location_assignment PIN_28 -to ad[6]
set_location_assignment PIN_26 -to ad[7]