📄 fft_01.mdl
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Points [20, 0; 0, -50]
DstBlock "FIFO_r"
DstPort 1
}
Line {
SrcBlock "FFT v1_0 "
SrcPort 2
Points [95, 0; 0, 50]
DstBlock "FIFO_i"
DstPort 1
}
Line {
SrcBlock "FFT v1_0 "
SrcPort 3
Points [60, 0; 0, 55; 80, 0]
Branch {
DstBlock "FIFO_i"
DstPort 2
}
Branch {
Points [0, -135]
DstBlock "FIFO_r"
DstPort 2
}
}
Line {
SrcBlock "Logical and"
SrcPort 1
Points [0, 0; 0, -10]
Branch {
Points [0, -35]
Branch {
DstBlock "FIFO_i"
DstPort 3
}
Branch {
Points [0, -135]
DstBlock "FIFO_r"
DstPort 3
}
}
Branch {
DstBlock "Down Sample2"
DstPort 1
}
}
Line {
SrcBlock "Down Sample2"
SrcPort 1
DstBlock "FFT_vout_out"
DstPort 1
}
Line {
SrcBlock "FIFO_i"
SrcPort 1
DstBlock "Down Sample1"
DstPort 1
}
Line {
SrcBlock "Down Sample"
SrcPort 1
DstBlock "FFt_Xk_r_out\n"
DstPort 1
}
Line {
SrcBlock "FIFO_r"
SrcPort 1
Points [65, 0; 0, 25]
DstBlock "Down Sample"
DstPort 1
}
Line {
SrcBlock "FIFO_r"
SrcPort 2
Points [35, 0; 0, 330]
DstBlock "Logical nor"
DstPort 2
}
Line {
SrcBlock "FIFO_i"
SrcPort 2
Points [10, 0; 0, 165]
DstBlock "Logical nor"
DstPort 1
}
Line {
SrcBlock "FIFO_r"
SrcPort 3
DstBlock "Term_r_%full"
DstPort 1
}
Line {
SrcBlock "FIFO_i"
SrcPort 3
Points [75, 0; 0, -20]
DstBlock "Term_i_%full"
DstPort 1
}
Line {
SrcBlock "FIFO_r"
SrcPort 4
Points [80, 0]
DstBlock "Term_r_full"
DstPort 1
}
Line {
SrcBlock "FFT v1_0 "
SrcPort 4
DstBlock "Term_done"
DstPort 1
}
Line {
SrcBlock "FFT v1_0 "
SrcPort 5
Points [15, 0; 0, 30]
DstBlock "Term_rfd"
DstPort 1
}
Line {
SrcBlock "FIFO_i"
SrcPort 4
DstBlock "Term_i_full"
DstPort 1
}
Line {
SrcBlock "Down Sample1"
SrcPort 1
DstBlock "FFT_Xk_i_out"
DstPort 1
}
Line {
SrcBlock "FFT_vin_in"
SrcPort 1
DstBlock "FFT v1_0 "
DstPort 3
}
Line {
SrcBlock "FFT_xn_i_in"
SrcPort 1
DstBlock "FFT v1_0 "
DstPort 2
}
Line {
SrcBlock "FFT_xn_r_in"
SrcPort 1
DstBlock "FFT v1_0 "
DstPort 1
}
}
}
Block {
BlockType SignalGenerator
Name "SG_xn_r"
Ports [0, 1]
Position [45, 50, 75, 80]
WaveForm "square"
Frequency "120"
}
Block {
BlockType Scope
Name "Scope_Xk_i"
Ports [1]
Position [780, 119, 810, 151]
Location [324, 449, 648, 688]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
YMin "-0.3"
YMax "0.3"
SaveName "ScopeData4"
DataFormat "StructureWithTime"
MaxDataPoints "500000"
}
Block {
BlockType Scope
Name "Scope_Xk_r"
Ports [1]
Position [780, 49, 810, 81]
Location [188, 390, 512, 629]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
DataFormat "StructureWithTime"
MaxDataPoints "500000"
}
Block {
BlockType Scope
Name "Scope_vin"
Ports [1]
Position [475, 394, 505, 426]
Location [188, 390, 512, 629]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
SaveName "ScopeData3"
DataFormat "StructureWithTime"
MaxDataPoints "500000"
}
Block {
BlockType Scope
Name "Scope_vout"
Ports [1]
Position [785, 189, 815, 221]
Location [188, 390, 512, 629]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
SaveName "ScopeData5"
DataFormat "StructureWithTime"
MaxDataPoints "500000"
}
Block {
BlockType Scope
Name "Scope_xn_i"
Ports [1]
Position [475, 329, 505, 361]
Location [188, 390, 512, 629]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
SaveName "ScopeData2"
DataFormat "StructureWithTime"
MaxDataPoints "500000"
}
Block {
BlockType Scope
Name "Scope_xn_r"
Ports [1]
Position [475, 269, 505, 301]
Location [188, 390, 987, 629]
Open off
NumInputPorts "1"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
SaveName "ScopeData1"
DataFormat "StructureWithTime"
MaxDataPoints "500000"
}
Block {
BlockType Reference
Name "Xk_i_out"
Ports [1, 1]
Position [680, 124, 735, 146]
SourceBlock "xbsIndex_r4/Gateway Out"
SourceType "Xilinx Gateway Out Block"
infoedit "Gateway out block. Converts Xilinx fixed point"
" inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Ha"
"rdware notes: In hardware these blocks become top level output ports or are "
"discarded, depending on how they are configured."
hdl_port on
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "gatewayout"
sg_icon_stat "55,22,1,1,white,yellow,0,9fe4cd0e"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 3"
"0 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18"
" 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 60 60 0 ],[0 20 20 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf4','"
"texmode','on');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf4'"
",'texmode','on');\nfprintf('','COMMENT: end icon text');\nfprintf('','COMMENT"
": Make no changes above this line -- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "Xk_r_out"
Ports [1, 1]
Position [680, 54, 735, 76]
SourceBlock "xbsIndex_r4/Gateway Out"
SourceType "Xilinx Gateway Out Block"
infoedit "Gateway out block. Converts Xilinx fixed point"
" inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Ha"
"rdware notes: In hardware these blocks become top level output ports or are "
"discarded, depending on how they are configured."
hdl_port on
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "20,20,411,338"
block_type "gatewayout"
sg_icon_stat "55,22,1,1,white,yellow,0,9fe4cd0e"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 3"
"0 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18"
" 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 60 60 0 ],[0 20 20 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf4','"
"texmode','on');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf4'"
",'texmode','on');\nfprintf('','COMMENT: end icon text');\nfprintf('','COMMENT"
": Make no changes above this line -- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "vin_in"
Ports [1, 1]
Position [130, 194, 185, 216]
SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type Simu"
"link integer, double and fixed point to Xilinx fixed point type.<P><P>Hardwa"
"re notes: In hardware these blocks become top level input ports."
arith_type "Boolean"
n_bits "16"
bin_pt "14"
period "1/12000"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0,0,0,0,0,0,0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "20,20,425,354"
block_type "gatewayin"
sg_icon_stat "55,22,1,1,white,yellow,0,9fe4cd0e"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 3"
"3 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18"
" 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 65 65 0 ],[0 20 20 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf4','"
"texmode','on');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf4'"
",'texmode','on');\nfprintf('','COMMENT: end icon text');\nfprintf('','COMMENT"
": Make no changes above this line -- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "vin_out"
Ports [1, 1]
Position [330, 399, 385, 421]
SourceBlock "xbsIndex_r4/Gateway Out"
SourceType "Xilinx Gateway Out Block"
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