fft_01.mdl

实现用systerm generation 完成fft变换。原理清晰

		Cell			"SupportNonInlinedSFcns"
		PropName		"DisabledProps"
	      }
	      Version		      "1.0.4"
	      TargetFcnLib	      "ansi_tfl_tmw.mat"
	      GenFloatMathFcnCalls    "ANSI_C"
	      UtilityFuncGeneration   "Auto"
	      GenerateFullHeader      on
	      GenerateSampleERTMain   off
	      IsPILTarget	      off
	      ModelReferenceCompliant on
	      IncludeMdlTerminateFcn  on
	      CombineOutputUpdateFcns off
	      SuppressErrorStatus     off
	      IncludeFileDelimiter    "Auto"
	      ERTCustomFileBanners    off
	      SupportAbsoluteTime     on
	      LogVarNameModifier      "rt_"
	      MatFileLogging	      on
	      MultiInstanceERTCode    off
	      SupportNonFinite	      on
	      SupportComplex	      on
	      PurelyIntegerCode	      off
	      SupportContinuousTime   on
	      SupportNonInlinedSFcns  on
	      ExtMode		      off
	      ExtModeStaticAlloc      off
	      ExtModeTesting	      off
	      ExtModeStaticAllocSize  1000000
	      ExtModeTransport	      0
	      ExtModeMexFile	      "ext_comm"
	      RTWCAPISignals	      off
	      RTWCAPIParams	      off
	      RTWCAPIStates	      off
	      GenerateASAP2	      off
	    }
	    PropName		    "Components"
	  }
	}
	PropName		"Components"
      }
      Name		      "Configuration"
      SimulationMode	      "normal"
      CurrentDlgPage	      "Solver"
    }
    PropName		    "ConfigurationSets"
  }
  Simulink.ConfigSet {
    $PropName		    "ActiveConfigurationSet"
    $ObjectID		    1
  }
  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  BlockParameterDefaults {
    Block {
      BlockType		      Constant
      Value		      "1"
      VectorParams1D	      on
      OutDataTypeMode	      "Inherit from 'Constant value'"
      OutDataType	      "sfix(16)"
      ConRadixGroup	      "Use specified scaling"
      OutScaling	      "2^0"
      SampleTime	      "inf"
    }
    Block {
      BlockType		      DiscretePulseGenerator
      PulseType		      "Sample based"
      TimeSource	      "Use simulation time"
      Amplitude		      "1"
      Period		      "2"
      PulseWidth	      "1"
      PhaseDelay	      "0"
      SampleTime	      "1"
      VectorParams1D	      on
    }
    Block {
      BlockType		      Inport
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      Interpolate	      on
    }
    Block {
      BlockType		      Outport
      Port		      "1"
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
    }
    Block {
      BlockType		      Scope
      Floating		      off
      ModelBased	      off
      TickLabels	      "OneTimeTick"
      ZoomMode		      "on"
      Grid		      "on"
      TimeRange		      "auto"
      YMin		      "-5"
      YMax		      "5"
      SaveToWorkspace	      off
      SaveName		      "ScopeData"
      LimitDataPoints	      on
      MaxDataPoints	      "5000"
      Decimation	      "1"
      SampleInput	      off
      SampleTime	      "0"
    }
    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      SFunctionModules	      "''"
      PortCounts	      "[]"
    }
    Block {
      BlockType		      SignalGenerator
      WaveForm		      "sine"
      TimeSource	      "Use simulation time"
      Amplitude		      "1"
      Frequency		      "1"
      Units		      "Hertz"
      VectorParams1D	      on
    }
    Block {
      BlockType		      SubSystem
      ShowPortLabels	      on
      Permissions	      "ReadWrite"
      PermitHierarchicalResolution "All"
      SystemSampleTime	      "-1"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
    Block {
      BlockType		      Terminator
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "fft_01"
    Location		    [2, 82, 1014, 721]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "A4"
    PaperUnits		    "centimeters"
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Reference
      Name		      " System Generator"
      Tag		      "genX"
      Ports		      []
      Position		      [92, 281, 143, 331]
      ShowName		      off
      AttributesFormatString  "System\\nGenerator"
      UserDataPersistent      on
      UserData		      "DataTag0"
      SourceBlock	      "xbsIndex_r4/ System Generator"
      SourceType	      "Xilinx System Generator"
      ShowPortLabels	      on
      xilinxfamily	      "Spartan3"
      part		      "xc3s1000"
      speed		      "-4"
      package		      "fg676"
      synthesis_tool	      "XST"
      directory		      "C:/MATLAB701/work/Dsp_/FFt"
      testbench		      off
      simulink_period	      "1/48000"
      sysclk_period	      "20"
      incr_netlist	      off
      trim_vbits	      "Everywhere in SubSystem"
      dbl_ovrd		      "According to Block Masks"
      core_generation	      "According to Block Masks"
      run_coregen	      off
      deprecated_control      off
      eval_field	      "0"
      block_type	      "sysgen"
    }
    Block {
      BlockType		      Constant
      Name		      "Const_vin"
      Position		      [45, 190, 75, 220]
    }
    Block {
      BlockType		      Constant
      Name		      "Const_xn_i"
      Position		      [50, 120, 80, 150]
      Value		      "0"
    }
    Block {
      BlockType		      SubSystem
      Name		      "FFT  Subsystem"
      Ports		      [3, 3]
      Position		      [390, 27, 565, 243]
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      System {
	Name			"FFT  Subsystem"
	Location		[2, 82, 1014, 704]
	Open			on
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "FFT_xn_r_in"
	  Position		  [55, 78, 85, 92]
	  Port			  "1"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "FFT_xn_i_in"
	  Position		  [55, 123, 85, 137]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "FFT_vin_in"
	  Position		  [55, 168, 85, 182]
	  Port			  "3"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "Clock Enable Probe"
	  Ports			  [1, 1]
	  Position		  [215, 361, 260, 389]
	  SourceBlock		  "xbsIndex_r4/Clock Enable Probe"
	  SourceType		  "Xilinx Clock Enable Probe Block"
	  infoedit		  "Clock enable extractor.  Produces a Boolean"
" output that mirrors the hardware clock enable associated with the input samp"
"le rate.<P><P>Hardware notes: in hardware this block costs nothing."
	  block_version		  "VER_STRING_GOES_HERE"
	  has_advanced_control	  "0"
	  sggui_pos		  "227,276,354,166"
	  block_type		  "ceprobe"
	  sg_icon_stat		  "45,28,1,1,white,blue,0,47c1520c"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics ')"
";\npatch([0 45 45 0 ],[0 0 28 28 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 "
"22 24 26 34 28 22 18 26 18 22 28 34 26 24 22 15 ],[3 8 15 22 27 27 25 27 27 2"
"1 27 23 15 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 0 45 45 0 ],[0 28 28"
" 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: b"
"egin icon text ');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf"
"4','texmode','on');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\"
"bf1','texmode','on');\ncolor('black');disp('');\nfprintf('','COMMENT: end ico"
"n text');\nfprintf('','COMMENT: Make no changes above this line -- machine ge"
"nerated code. ');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant_FFT_inv"
	  Ports			  [0, 1]
	  Position		  [50, 207, 105, 233]
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Boolean"
	  const			  "0"
	  n_bits		  "16"
	  bin_pt		  "14"
	  explicit_period	  on
	  period		  "1/12000"
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  block_version		  "VER_STRING_GOES_HERE"
	  has_advanced_control	  "0"
	  sggui_pos		  "53,82,467,304"
	  block_type		  "constant"
	  sg_icon_stat		  "55,26,0,1,white,blue,0,fce4d199"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics ')"
";\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 "
"27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 1"
"7 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 26 26"
" 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: b"
"egin icon text ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\b"
"f4','texmode','on');\nfprintf('','COMMENT: end icon text');\nfprintf('','COMM"
"ENT: Make no changes above this line -- machine generated code. ');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Down Sample"
	  Ports			  [1, 1]
	  Position		  [645, 22, 705, 78]
	  SourceBlock		  "xbsIndex_r4/Down Sample"
	  SourceType		  "Xilinx Down Sampler Block"
	  infoedit		  "Hardware notes: Sample and Latency controls"
" determine the hardware implementation.  The cost in hardware of different im"
"plementations varies considerably; press Help for details."
	  sample_ratio		  "4"
	  sample_phase		  "Last Value of Frame  (most efficient)"
	  en			  off
	  latency		  "1"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  block_version		  "VER_STRING_GOES_HERE"
	  has_advanced_control	  "0"
	  sggui_pos		  "163,133,425,300"
	  block_type		  "dsamp"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,5e9de106"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics ')"
";\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30"