📄 at89x52.lst
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C51 COMPILER V6.12 AT89X52 05/05/2008 10:44:12 PAGE 1
C51 COMPILER V6.12, COMPILATION OF MODULE AT89X52
OBJECT MODULE PLACED IN .\AT89X52.obj
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE C:\Keil\C51\INC\Atmel\AT89X52.H DEBUG OBJECTEXTEND PRINT(.\AT89X52.lst) OBJ
-ECT(.\AT89X52.obj)
stmt level source
1 /*--------------------------------------------------------------------------
2 AT89X52.H
3
4 Header file for the low voltage Flash Atmel AT89C52 and AT89LV52.
5 Copyright (c) 1995-1996 Keil Software, Inc. All rights reserved.
6 --------------------------------------------------------------------------*/
7
8 #ifndef AT89X52_HEADER_FILE
9 #define AT89X52_HEADER_FILE 1
10
11 /*------------------------------------------------
12 Byte Registers
13 ------------------------------------------------*/
14 sfr P0 = 0x80;
15 sfr SP = 0x81;
16 sfr DPL = 0x82;
17 sfr DPH = 0x83;
18 sfr PCON = 0x87;
19 sfr TCON = 0x88;
20 sfr TMOD = 0x89;
21 sfr TL0 = 0x8A;
22 sfr TL1 = 0x8B;
23 sfr TH0 = 0x8C;
24 sfr TH1 = 0x8D;
25 sfr P1 = 0x90;
26 sfr SCON = 0x98;
27 sfr SBUF = 0x99;
28 sfr P2 = 0xA0;
29 sfr IE = 0xA8;
30 sfr P3 = 0xB0;
31 sfr IP = 0xB8;
32 sfr T2CON = 0xC8;
33 sfr T2MOD = 0xC9;
34 sfr RCAP2L = 0xCA;
35 sfr RCAP2H = 0xCB;
36 sfr TL2 = 0xCC;
37 sfr TH2 = 0xCD;
38 sfr PSW = 0xD0;
39 sfr ACC = 0xE0;
40 sfr B = 0xF0;
41
42 /*------------------------------------------------
43 P0 Bit Registers
44 ------------------------------------------------*/
45 sbit P0_0 = 0x80;
46 sbit P0_1 = 0x81;
47 sbit P0_2 = 0x82;
48 sbit P0_3 = 0x83;
49 sbit P0_4 = 0x84;
50 sbit P0_5 = 0x85;
51 sbit P0_6 = 0x86;
52 sbit P0_7 = 0x87;
53
54 /*------------------------------------------------
C51 COMPILER V6.12 AT89X52 05/05/2008 10:44:12 PAGE 2
55 PCON Bit Values
56 ------------------------------------------------*/
57 #define IDL_ 0x01
58
59 #define STOP_ 0x02
60 #define PD_ 0x02 /* Alternate definition */
61
62 #define GF0_ 0x04
63 #define GF1_ 0x08
64 #define SMOD_ 0x80
65
66 /*------------------------------------------------
67 TCON Bit Registers
68 ------------------------------------------------*/
69 sbit IT0 = 0x88;
70 sbit IE0 = 0x89;
71 sbit IT1 = 0x8A;
72 sbit IE1 = 0x8B;
73 sbit TR0 = 0x8C;
74 sbit TF0 = 0x8D;
75 sbit TR1 = 0x8E;
76 sbit TF1 = 0x8F;
77
78 /*------------------------------------------------
79 TMOD Bit Values
80 ------------------------------------------------*/
81 #define T0_M0_ 0x01
82 #define T0_M1_ 0x02
83 #define T0_CT_ 0x04
84 #define T0_GATE_ 0x08
85 #define T1_M0_ 0x10
86 #define T1_M1_ 0x20
87 #define T1_CT_ 0x40
88 #define T1_GATE_ 0x80
89
90 #define T1_MASK_ 0xF0
91 #define T0_MASK_ 0x0F
92
93 /*------------------------------------------------
94 P1 Bit Registers
95 ------------------------------------------------*/
96 sbit P1_0 = 0x90;
97 sbit P1_1 = 0x91;
98 sbit P1_2 = 0x92;
99 sbit P1_3 = 0x93;
100 sbit P1_4 = 0x94;
101 sbit P1_5 = 0x95;
102 sbit P1_6 = 0x96;
103 sbit P1_7 = 0x97;
104
105 sbit T2 = 0x90; /* External input to Timer/Counter 2, clock out */
106 sbit T2EX = 0x91; /* Timer/Counter 2 capture/reload trigger & dir ctl */
107
108 /*------------------------------------------------
109 SCON Bit Registers
110 ------------------------------------------------*/
111 sbit RI = 0x98;
112 sbit TI = 0x99;
113 sbit RB8 = 0x9A;
114 sbit TB8 = 0x9B;
115 sbit REN = 0x9C;
116 sbit SM2 = 0x9D;
C51 COMPILER V6.12 AT89X52 05/05/2008 10:44:12 PAGE 3
117 sbit SM1 = 0x9E;
118 sbit SM0 = 0x9F;
119
120 /*------------------------------------------------
121 P2 Bit Registers
122 ------------------------------------------------*/
123 sbit P2_0 = 0xA0;
124 sbit P2_1 = 0xA1;
125 sbit P2_2 = 0xA2;
126 sbit P2_3 = 0xA3;
127 sbit P2_4 = 0xA4;
128 sbit P2_5 = 0xA5;
129 sbit P2_6 = 0xA6;
130 sbit P2_7 = 0xA7;
131
132 /*------------------------------------------------
133 IE Bit Registers
134 ------------------------------------------------*/
135 sbit EX0 = 0xA8; /* 1=Enable External interrupt 0 */
136 sbit ET0 = 0xA9; /* 1=Enable Timer 0 interrupt */
137 sbit EX1 = 0xAA; /* 1=Enable External interrupt 1 */
138 sbit ET1 = 0xAB; /* 1=Enable Timer 1 interrupt */
139 sbit ES = 0xAC; /* 1=Enable Serial port interrupt */
140 sbit ET2 = 0xAD; /* 1=Enable Timer 2 interrupt */
141
142 sbit EA = 0xAF; /* 0=Disable all interrupts */
143
144 /*------------------------------------------------
145 P3 Bit Registers (Mnemonics & Ports)
146 ------------------------------------------------*/
147 sbit P3_0 = 0xB0;
148 sbit P3_1 = 0xB1;
149 sbit P3_2 = 0xB2;
150 sbit P3_3 = 0xB3;
151 sbit P3_4 = 0xB4;
152 sbit P3_5 = 0xB5;
153 sbit P3_6 = 0xB6;
154 sbit P3_7 = 0xB7;
155
156 sbit RXD = 0xB0; /* Serial data input */
157 sbit TXD = 0xB1; /* Serial data output */
158 sbit INT0 = 0xB2; /* External interrupt 0 */
159 sbit INT1 = 0xB3; /* External interrupt 1 */
160 sbit T0 = 0xB4; /* Timer 0 external input */
161 sbit T1 = 0xB5; /* Timer 1 external input */
162 sbit WR = 0xB6; /* External data memory write strobe */
163 sbit RD = 0xB7; /* External data memory read strobe */
164
165 /*------------------------------------------------
166 IP Bit Registers
167 ------------------------------------------------*/
168 sbit PX0 = 0xB8;
169 sbit PT0 = 0xB9;
170 sbit PX1 = 0xBA;
171 sbit PT1 = 0xBB;
172 sbit PS = 0xBC;
173 sbit PT2 = 0xBD;
174
175 /*------------------------------------------------
176 T2CON Bit Registers
177 ------------------------------------------------*/
178 sbit CP_RL2= 0xC8; /* 0=Reload, 1=Capture select */
C51 COMPILER V6.12 AT89X52 05/05/2008 10:44:12 PAGE 4
179 sbit C_T2 = 0xC9; /* 0=Timer, 1=Counter */
180 sbit TR2 = 0xCA; /* 0=Stop timer, 1=Start timer */
181 sbit EXEN2= 0xCB; /* Timer 2 external enable */
182 sbit TCLK = 0xCC; /* 0=Serial clock uses Timer 1 overflow, 1=Timer 2 */
183 sbit RCLK = 0xCD; /* 0=Serial clock uses Timer 1 overflow, 1=Timer 2 */
184 sbit EXF2 = 0xCE; /* Timer 2 external flag */
185 sbit TF2 = 0xCF; /* Timer 2 overflow flag */
186
187 /*------------------------------------------------
188 T2MOD Bit Values
189 ------------------------------------------------*/
190 #define DCEN_ 0x01 /* 1=Timer 2 can be configured as up/down counter */
191 #define T2OE_ 0x02 /* Timer 2 output enable */
192
193 /*------------------------------------------------
194 PSW Bit Registers
195 ------------------------------------------------*/
196 sbit P = 0xD0;
197 sbit FL = 0xD1;
198 sbit OV = 0xD2;
199 sbit RS0 = 0xD3;
200 sbit RS1 = 0xD4;
201 sbit F0 = 0xD5;
202 sbit AC = 0xD6;
203 sbit CY = 0xD7;
204
205 /*------------------------------------------------
206 Interrupt Vectors:
207 Interrupt Address = (Number * 8) + 3
208 ------------------------------------------------*/
209 #define IE0_VECTOR 0 /* 0x03 External Interrupt 0 */
210 #define TF0_VECTOR 1 /* 0x0B Timer 0 */
211 #define IE1_VECTOR 2 /* 0x13 External Interrupt 1 */
212 #define TF1_VECTOR 3 /* 0x1B Timer 1 */
213 #define SIO_VECTOR 4 /* 0x23 Serial port */
214
215 #define TF2_VECTOR 5 /* 0x2B Timer 2 */
216 #define EX2_VECTOR 5 /* 0x2B External Interrupt 2 */
217
218 /*------------------------------------------------
219 ------------------------------------------------*/
220 #endif
221
222
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = ---- ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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