_info

用vhal在qurtusII 7.2 实现的cpsk.dpsk.fsk.ask 四种方式可控制调制方式

m255
13
cModel Technology
dD:\altera\72\modelsim_ae\examples
Ealt3pram
w1190857576
DP work altera_mf_hint_evaluation g1_P>M@<J[5UZWTofa`5L2
DE work altsyncram 54EiARZeBiC[N[zzc>^BL1
DP work altera_common_conversion <XPhiZ[Qn=^ZB;m1i8ROG1
DP work altera_device_families 3@Da@Iz=jma8_<Lzg<A;k2
DP std textio _JFaH0dHhZY?i]8<G2OFZ3
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
dD:\altera\lianxi\heilang1\sin_out\simulation\modelsim
FD:/altera/lianxi/heilang1/sin_out/simulation/modelsim/altera_mf_87.vhd
l0
L42544
VMO676V33`J0j^h;GJC;H`1
OV;C;6.1g;31
32
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Abehavior
DE work altsyncram 54EiARZeBiC[N[zzc>^BL1
DP work altera_mf_hint_evaluation g1_P>M@<J[5UZWTofa`5L2
DP work altera_common_conversion <XPhiZ[Qn=^ZB;m1i8ROG1
DP work altera_device_families 3@Da@Iz=jma8_<Lzg<A;k2
DP std textio _JFaH0dHhZY?i]8<G2OFZ3
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work alt3pram MO676V33`J0j^h;GJC;H`1
l42884
L42595
VBDJY8]?_;^KGFm`aAgY1@1
OV;C;6.1g;31
32
M7 ieee std_logic_1164
M6 ieee std_logic_arith
M5 ieee std_logic_unsigned
M4 std textio
M3 work altera_device_families
M2 work altera_common_conversion
M1 work altera_mf_hint_evaluation
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Ealtaccumulate
w1190857576
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
dD:\altera\lianxi\heilang1\sin_out\simulation\modelsim
FD:/altera/lianxi/heilang1/sin_out/simulation/modelsim/altera_mf_87.vhd
l0
L16410
VC2_<l184PnGmkdoblhIIo3
OV;C;6.1g;31
32
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Abehaviour
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work altaccumulate C2_<l184PnGmkdoblhIIo3
l16457
L16443
VP@XH0bz9S8V=Ii6iZCDBB2
OV;C;6.1g;31
32
M2 ieee std_logic_1164
M1 ieee std_logic_arith
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Ealtcam
w1190857576
DP work altera_common_conversion <XPhiZ[Qn=^ZB;m1i8ROG1
DP std textio _JFaH0dHhZY?i]8<G2OFZ3
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
dD:\altera\lianxi\heilang1\sin_out\simulation\modelsim
FD:/altera/lianxi/heilang1/sin_out/simulation/modelsim/altera_mf_87.vhd
l0
L35917
Vo_Z6?ZUfhZh35cKIVaHAB2
OV;C;6.1g;31
32
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Abehave
DP work altera_common_conversion <XPhiZ[Qn=^ZB;m1i8ROG1
DP std textio _JFaH0dHhZY?i]8<G2OFZ3
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work altcam o_Z6?ZUfhZh35cKIVaHAB2
l36620
L36569
V;cJh883IIYb;:Hd@7FJSg2
OV;C;6.1g;31
32
M5 ieee std_logic_1164
M4 ieee std_logic_arith
M3 ieee std_logic_unsigned
M2 std textio
M1 work altera_common_conversion
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Ealtcdr_rx
w1190857576
DE work hssi_fifo VFGZL=dXY]9;JXD93jC:S3
DE work hssi_rx l42VLWOamX;Ll?1j8]c2E3
DE work hssi_pll ;n@FCbm`k^@4Sa3O1G=TL2
DP work mf_pllpack >NV<jYWY9T:>>Qoc77o1z0
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
dD:\altera\lianxi\heilang1\sin_out\simulation\modelsim
FD:/altera/lianxi/heilang1/sin_out/simulation/modelsim/altera_mf_87.vhd
l0
L29270
VohXR5EzA`AjXPbOa9@L>j3
OV;C;6.1g;31
32
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Astruct
DE work hssi_fifo VFGZL=dXY]9;JXD93jC:S3
DE work hssi_rx l42VLWOamX;Ll?1j8]c2E3
DE work hssi_pll ;n@FCbm`k^@4Sa3O1G=TL2
DP work mf_pllpack >NV<jYWY9T:>>Qoc77o1z0
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work altcdr_rx ohXR5EzA`AjXPbOa9@L>j3
l29369
L29302
V97Z_i1@M5m;fil=[X[2I43
OV;C;6.1g;31
32
M2 ieee std_logic_1164
M1 work mf_pllpack
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Ealtcdr_tx
w1190857576
DE work hssi_fifo VFGZL=dXY]9;JXD93jC:S3
DE work hssi_tx STZiDAdC6ofEP=jPJIXD;3
DE work hssi_pll ;n@FCbm`k^@4Sa3O1G=TL2
DP work mf_pllpack >NV<jYWY9T:>>Qoc77o1z0
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
dD:\altera\lianxi\heilang1\sin_out\simulation\modelsim
FD:/altera/lianxi/heilang1/sin_out/simulation/modelsim/altera_mf_87.vhd
l0
L29492
VJIYScM`0WIz5`C9e7bDCG1
OV;C;6.1g;31
32
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Astruct
DE work hssi_fifo VFGZL=dXY]9;JXD93jC:S3
DE work hssi_tx STZiDAdC6ofEP=jPJIXD;3
DE work hssi_pll ;n@FCbm`k^@4Sa3O1G=TL2
DP work mf_pllpack >NV<jYWY9T:>>Qoc77o1z0
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work altcdr_tx JIYScM`0WIz5`C9e7bDCG1
l29579
L29520
VTOl[>zkJ6NblM0M4i>bMU0
OV;C;6.1g;31
32
M2 ieee std_logic_1164
M1 work mf_pllpack
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Ealtclklock
w1190857576
DP work altera_device_families 3@Da@Iz=jma8_<Lzg<A;k2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
dD:\altera\lianxi\heilang1\sin_out\simulation\modelsim
FD:/altera/lianxi/heilang1/sin_out/simulation/modelsim/altera_mf_87.vhd
l0
L26886
VGV91N:I[GOZ`]^R_S9fS=1
OV;C;6.1g;31
32
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Abehavior
DP work altera_device_families 3@Da@Iz=jma8_<Lzg<A;k2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work altclklock GV91N:I[GOZ`]^R_S9fS=1
l27008
L26998
VY?mD>ZFYlZPA2ZHk;Z9md0
OV;C;6.1g;31
32
M2 ieee std_logic_1164
M1 work altera_device_families
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Ealtddio_bidir
w1190857576
DE work altddio_out RmzjP`EYhW;i=4E<`jSNP2
DP work altera_device_families 3@Da@Iz=jma8_<Lzg<A;k2
DE work altddio_in PHBBolQeBTL24`O?M0W8P2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
dD:\altera\lianxi\heilang1\sin_out\simulation\modelsim
FD:/altera/lianxi/heilang1/sin_out/simulation/modelsim/altera_mf_87.vhd
l0
L28004
V66:B3SbkC69b[h=fNYfl22
OV;C;6.1g;31
32
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Astruct
DE work altddio_out RmzjP`EYhW;i=4E<`jSNP2
DE work altddio_in PHBBolQeBTL24`O?M0W8P2
DP work altera_device_families 3@Da@Iz=jma8_<Lzg<A;k2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work altddio_bidir 66:B3SbkC69b[h=fNYfl22
l28104
L28059
Vc_WOc_`k3L=fDZInB2njP0
OV;C;6.1g;31
32
M2 ieee std_logic_1164
M1 work altera_device_families
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Ealtddio_in
w1190857576
DP work altera_device_families 3@Da@Iz=jma8_<Lzg<A;k2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
dD:\altera\lianxi\heilang1\sin_out\simulation\modelsim
FD:/altera/lianxi/heilang1/sin_out/simulation/modelsim/altera_mf_87.vhd
l0
L27587
VPHBBolQeBTL24`O?M0W8P2
OV;C;6.1g;31
32
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Abehave
DP work altera_device_families 3@Da@Iz=jma8_<Lzg<A;k2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work altddio_in PHBBolQeBTL24`O?M0W8P2
l27615
L27614
V:;ZVL=hm43W@kzo=UB92P1
OV;C;6.1g;31
32
M2 ieee std_logic_1164
M1 work altera_device_families
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Ealtddio_out
w1190857576
DP work altera_device_families 3@Da@Iz=jma8_<Lzg<A;k2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
dD:\altera\lianxi\heilang1\sin_out\simulation\modelsim
FD:/altera/lianxi/heilang1/sin_out/simulation/modelsim/altera_mf_87.vhd
l0
L27801
VRmzjP`EYhW;i=4E<`jSNP2
OV;C;6.1g;31
32
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Abehave
DP work altera_device_families 3@Da@Iz=jma8_<Lzg<A;k2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work altddio_out RmzjP`EYhW;i=4E<`jSNP2
l27849
L27834
VGQFJ8[R>i2=K6aT3DDMkH2
OV;C;6.1g;31
32
M2 ieee std_logic_1164
M1 work altera_device_families
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Ealtdpram
w1190857576
DP work altera_common_conversion <XPhiZ[Qn=^ZB;m1i8ROG1
DP work altera_device_families 3@Da@Iz=jma8_<Lzg<A;k2
DP std textio _JFaH0dHhZY?i]8<G2OFZ3
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
dD:\altera\lianxi\heilang1\sin_out\simulation\modelsim
FD:/altera/lianxi/heilang1/sin_out/simulation/modelsim/altera_mf_87.vhd
l0
L38364
VjVEPfE2k[:R9DLRm58ZDL3
OV;C;6.1g;31
32
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Abehavior
DP work altera_common_conversion <XPhiZ[Qn=^ZB;m1i8ROG1
DP work altera_device_families 3@Da@Iz=jma8_<Lzg<A;k2
DP std textio _JFaH0dHhZY?i]8<G2OFZ3
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work altdpram jVEPfE2k[:R9DLRm58ZDL3
l38465
L38410
V^AgnhQMA8T=3d8o:cCQCZ2
OV;C;6.1g;31
32
M6 ieee std_logic_1164
M5 ieee std_logic_arith
M4 ieee std_logic_unsigned
M3 std textio
M2 work altera_device_families
M1 work altera_common_conversion
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Paltera_common_conversion
DP std textio _JFaH0dHhZY?i]8<G2OFZ3
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
w1190857576
dD:\altera\lianxi\heilang1\sin_out\simulation\modelsim
FD:/altera/lianxi/heilang1/sin_out/simulation/modelsim/altera_mf_87.vhd
l0
L43
V<XPhiZ[Qn=^ZB;m1i8ROG1
OV;C;6.1g;31
32
b1
M2 ieee std_logic_1164
M1 std textio
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Bbody
DB work altera_common_conversion <XPhiZ[Qn=^ZB;m1i8ROG1
DP std textio _JFaH0dHhZY?i]8<G2OFZ3
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
l0
L43
VNAU]7UYZIFamH68da>?102
OV;C;6.1g;31
32
M2 ieee std_logic_1164
M1 std textio
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
nbody
Paltera_device_families
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
w1190857576
dD:\altera\lianxi\heilang1\sin_out\simulation\modelsim
FD:/altera/lianxi/heilang1/sin_out/simulation/modelsim/altera_mf_87.vhd
l0
L418
V3@Da@Iz=jma8_<Lzg<A;k2
OV;C;6.1g;31
32
b1
M1 ieee std_logic_1164
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Bbody
DB work altera_device_families 3@Da@Iz=jma8_<Lzg<A;k2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
l0
L418
V8YHJDC_B4@b9?j]O;XQFT3
OV;C;6.1g;31
32
M1 ieee std_logic_1164
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
nbody
Paltera_mf_hint_evaluation
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
w1190857576
dD:\altera\lianxi\heilang1\sin_out\simulation\modelsim
FD:/altera/lianxi/heilang1/sin_out/simulation/modelsim/altera_mf_87.vhd
l0
L331
Vg1_P>M@<J[5UZWTofa`5L2
OV;C;6.1g;31
32
b1
M1 ieee std_logic_1164
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Bbody
DB work altera_mf_hint_evaluation g1_P>M@<J[5UZWTofa`5L2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
l0
L331
VfWY>bBWTM]dO4N@Vo3R?m2
OV;C;6.1g;31
32
M1 ieee std_logic_1164
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
nbody
Ealtfp_mult
w1190857576
DP std textio _JFaH0dHhZY?i]8<G2OFZ3
DP work altera_common_conversion <XPhiZ[Qn=^ZB;m1i8ROG1
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
dD:\altera\lianxi\heilang1\sin_out\simulation\modelsim
FD:/altera/lianxi/heilang1/sin_out/simulation/modelsim/altera_mf_87.vhd
l0
L26043
V^:ZUQ5FaNGe62So?fRQeS2
OV;C;6.1g;31
32
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Abehavior
DP std textio _JFaH0dHhZY?i]8<G2OFZ3
DP work altera_common_conversion <XPhiZ[Qn=^ZB;m1i8ROG1
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work altfp_mult ^:ZUQ5FaNGe62So?fRQeS2
l26186
L26090
V=Ih9mQ`5gjWB033ll<?BG3
OV;C;6.1g;31
32
M4 ieee std_logic_1164
M3 ieee std_logic_arith
M2 work altera_common_conversion
M1 std textio
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Ealtlvds_rx
w1190857576
DE work stratixiii_lvds_rx 2QKV2V9fKU>OejfLU]oRA3
DE work flexible_lvds_rx MN2`JNBmLPHISOT^?;3C^2
DE work stratixii_lvds_rx AAe]^85FC04>;C0^>W8zj0
DE work altclklock GV91N:I[GOZ`]^R_S9fS=1
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DE work mf_stratixiii_pll T5;0Oa@A7HP^jk`5nQe5z2
DE work mf_stratixii_pll ]fbj5QhX^zi6QNWLKhhD^2
DP work mf_pllpack >NV<jYWY9T:>>Qoc77o1z0
DP std textio _JFaH0dHhZY?i]8<G2OFZ3
DE work mf_stratix_pll gM01S:R3>TbnnL;L4hD6T1
DP work altera_device_families 3@Da@Iz=jma8_<Lzg<A;k2
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
dD:\altera\lianxi\heilang1\sin_out\simulation\modelsim
FD:/altera/lianxi/heilang1/sin_out/simulation/modelsim/altera_mf_87.vhd
l0
L31170
Vh2RHKU^8QzK^77I40k5090
OV;C;6.1g;31
32
o-work work -O0
tExplicit 1 GenerateLoopIterationMax 100000
Abehavior
DE work stratixiii_lvds_rx 2QKV2V9fKU>OejfLU]oRA3
DE work flexible_lvds_rx MN2`JNBmLPHISOT^?;3C^2
DE work stratixii_lvds_rx AAe]^85FC04>;C0^>W8zj0
DE work altclklock GV91N:I[GOZ`]^R_S9fS=1
DE work mf_stratixiii_pll T5;0Oa@A7HP^jk`5nQe5z2
DE work mf_stratixii_pll ]fbj5QhX^zi6QNWLKhhD^2
DE work mf_stratix_pll gM01S:R3>TbnnL;L4hD6T1
DP ieee std_logic_unsigned =:F>A4m7i`0z3e0XK^PIX0
DP work mf_pllpack >NV<jYWY9T:>>Qoc77o1z0
DP std textio _JFaH0dHhZY?i]8<G2OFZ3
DP work altera_device_families 3@Da@Iz=jma8_<Lzg<A;k2
DP ieee std_logic_arith N1b?3<a_g2AOk_0Ie>0F:2
DP ieee std_logic_1164 ChagfbCXBFdaC62b9Y:;<1
DE work altlvds_rx h2RHKU^8QzK^77I40k5090
l32011
L31253