uart.c

uboot底层驱动

/*************************************************************************************
*	Copyright (c) 2005 by National ASIC System Engineering Research Center.
*	PROPRIETARY RIGHTS of ASIC are involved in the subject matter of this 
*	material.  All manufacturing, reproduction, use, and sales rights 
*	pertaining to this subject matter are governed by the license agreement.
*	The recipient of this software implicitly accepts the terms of the license.
*
*	File Name: uart.c
*
*	File Description:
*			The file consists of the function used to config uart
*
*	Function Description:
*		uart_reset_value_test()			
*								check uart registers reset value
*
*		HA_InitUart1(U32 clk, U32 baud, U32 bits, U32 triger)
*								 initiate UART
*								
*
*		ER en_re_int(U32)
*								enable and disable the recieve int and the transmit int
*               thr_isr_uart0(void)
                                                                interrupt handler for UART1
                rda_isr_uart0(void) 
                                                                interrupt handler
                int_serv_uart0()
                                                                UART0 interrupt service
*	Created by Michael <[e-mail]>, 2005-03-21
**************************************************************************************/


#include "uart.h"


#define  write_reg(ADDR, DATE)  (*(unsigned  *)(ADDR) = (unsigned )(DATE))

#define read_reg(ADDR)	(*(volatile unsigned  *)(ADDR))

#define E_OK  0

void delay(void)
{
	int i;
	for (i=0; i < 20000; i++) 
	 ;
}
 

int init_uart0(U32 sysclk, U32 baudrate, U32 databit,U32 trigerlevel)
{
    U32 baud, bit, triger, baudh, baudl;
    baud  = sysclk/16/baudrate;//￡?
    baudh = baud >> 8;//2¨ì??ê??8???3?μ
    baudl = baud & 0xff;//2¨ì??êμí8???3?μ
    
    switch(databit)//?ù?Yêy?Y??′óD??D??￡?
    //?????é????ó|2?í?μ?êy?Y±èì?êy￡o00￡¨5bits￡?￡?01￡¨6bits￡?￡?10￡¨7bits￡?￡?11￡¨8bits￡?
    {
    	case 5: bit = 0x80;
    	     break;
    	     
    	case 6: bit = 0x81;
    	     break;
    	       
    	case 7: bit = 0x82;
    	     break;
    	     
    	case 8: bit = 0x83;
    	     break;
    	
    	default: ;
    	     break;             	  	
    }	
    
    write_reg(UART0_LCR, bit);  //divisor latch±?·??ê￡?í¨1yê?è?μ?êy?Ybitμú8???a1????
    
    write_reg(UART0_DLH, baudh);//??????oóμ?2¨ì??êD′è???8??
    write_reg(UART0_DLL, baudl);//??????oóμ?2¨ì??êD′è?μí8??
    read_reg(UART0_LCR) &= (~(0x1 << 7));  //í¨1yUART0_LCRμú8??oí0?àó???0￡?1?±?2¨ì??ê·??ê￡?
    //×aμ???í¨??′??÷μ?·??ê￡??á′?íê3éμ?êy?Yμ?3?ê??ˉ
    
    switch(trigerlevel)//′￥·￠??3?ê??ˉ￡??¨ò?transmitter FIFOμ?trigger level￡o00￡¨0byte￡?￡?
    //01￡¨2byte￡?￡?10￡¨4byte￡?￡?11￡¨8byte￡?
    {
    	case 1:  triger = 0x0;
    	     break;
    	     
    	case 4:  triger = 0x1;
    	     break;
    	     
    	case 8:  triger = 0x2;
    	     break;
    	     
    	case 14: triger = 0x3;
    	     break;
    	
    }
    
    triger = (triger << 6);
    
    write_reg(UART0_FCR, 0x06);
    write_reg(UART0_FCR, 0x00);

    
    //write_reg(UART0_IER, 0x04);//′ò?a?óê?FIFO′￥·￠???D??ê1?ü
    
    return E_OK;
}


int uart_getchar(unsigned int UART_BASE,char* ch)
{
	//while((read_reg(UART0_LSR)&0x20)==0) ;
	
	   		  /***portB6  置零 收******/
  delay();
  *(volatile unsigned long *)PORTB_DIR &= ~(0x1 << 6);
  *(volatile unsigned long *)PORTB_SEL |= 0x1<<6;		
  *(volatile unsigned long *)PORTB_DATA &= ~(0x1 << 6);
   // *(volatile unsigned long *)PORTB_DATA |= 0x1 << 6;


   while((read_reg(UART0_LSR)&0x01)==0) ;

    *ch= read_reg(UART0_RBR);//?áè??óê?FIFOà?μ?êy?Y
    return E_OK;
}


int uart_putchar(unsigned int UART_BASE,char ch )
{

  
  delay();
 
 //   while((read_reg(UART0_LSR)&0x01)==0) ;
     
  		 /***portB6  置一 发******/
  *(volatile unsigned long *)PORTB_DIR &= ~(0x1 << 6);
  *(volatile unsigned long *)PORTB_SEL |= 0x1<<6;		
  //*(volatile unsigned long *)PORTB_DATA &= ~(0x1 << 6);
  *(volatile unsigned long *)PORTB_DATA |= 0x1 << 6;
  while((read_reg(UART0_LSR)&0x20)==0) ;
     	write_reg(UART0_THR,(U32)ch);//°?òa·￠?íμ?êy?Y·?è?′?ê?FIFO    
    return E_OK;
}