uboot.s

uboot底层驱动

;********************************************************************************************
;*filename:			boot.s						
;*author:			WUER xiao <[e-mail]>
;*create date:		2005-5-10 16:25                                                                      
;*description:	    This file is used for 16 bit NOR FLASH bootloader                                                              
;*modify history:	                                                                      
;*misc:           
;********************************************************************************************
F_Bit		EQU 	0x40
Mode_Svc	EQU	0x13
 import c_entry
         


	AREA BOOTLOADER, CODE, READONLY                                                     
	ENTRY                           ; Mark first instruction to execute 
	
	b	reset
    b   .	
    b   .
    b   .
    b   .
    b   .
    b   .

  ;
  ; set the cpu to SVC32 mode

reset	
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0x13
	msr	cpsr_cxsf,r0
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	
  ;  WRITE(0X10003008, 0x06)
    ldr r1, =0x10003008
    ldr r2, =0x06
    str r2, [r1]
	
	ldr  r1, =0x10002014
	ldr  r2, =0xffffffff
	str  r2, [ r1 ]
	
	ldr r1, =0x100030a4
	ldr r2, [r1]
	
	ldr r1, =0x1000300c
	ldr r2, [r1]
	
	ldr r1, =0x10003020
	ldr r2, [r1]
	
	ldr r1, =0x10003034
	ldr r2, [r1]
	
	ldr r1, =0x10003048
	ldr r2, [r1]
	
	
	ldr r1, =0x10003008
    ldr r2, =0x06
    str r2, [r1]
    
    
        ldr r1, =0x1000301c
    ldr r2, =0x06
    str r2, [r1]
    
        ldr r1, =0x10003030
    ldr r2, =0x06
    str r2, [r1]
    
        ldr r1, =0x10003044
    ldr r2, =0x06
    str r2, [r1]
	
	ldr r1, =0x10004014
	ldr r2, [r1]
	
	ldr r1, =0x10005014
	ldr r2, [r1]
	
	ldr r1, =0x10004008
	ldr r2, [r1]
	
	ldr r1, =0x10005008
	ldr r2, [r1]
	
	
	ldr r1, =0x10004008
	ldr r2, [r1]
	bic r2, r2,#0x6
	orr r2, r2,#0x6
	str r2, [ r1 ]
	
	ldr r1, =0x10005008
	str r2, [ r1 ]
	
	
	
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

	;配置16位CSA Nor Flash
                          
	ldr		r1, =0x11000000        ;THE ADD OF EMIADDR_SMCONF
	ldr		r2, =0xB91311FF        ;cm:8019的片选要使能 
	str		r2, [ r1 ]

	ldr		r1, =0x11000014        ;THE ADD OF EMIADDR_SMCONF1
	ldr		r2, =0x01004077	
	str		r2, [ r1 ]

	ldr		r1, =0x11000018        ;THE ADD OF EMIADDR_SMCONF2
	ldr		r2, =0x80018500
	str		r2, [ r1 ]

	
;配置工作频率为75MHz
	
	ldr		r1, =0x1000100c
	ldr		r2, =0x1ffff
	str		r2,[r1]
	        	
	ldr		r1, =0x10001014
	ldr		r2, =0x1
	str		r2,[r1]
	        	
	ldr		r1, =0x10001000
	;ldr		r2, =0x018000cd
	ldr     r2, =0x00d200cd
	str		r2,[r1]
	        	
	ldr		r1, =0x10001004
	;ldr		r2, =0X238
	ldr		r2, =0X23c

	str		r2,[r1]
	        	
	ldr		r1, =0x10001004
	;ldr		r2, =0X1238
	ldr		r2, =0X123c

	str		r2,[r1]
	
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	ldr		r1, =0x1000b06c
	ldr		r2, =0x10
	str		r2,[r1]
	
	ldr		r1, =0x1000b068
	ldr		r2, =0x0
	str		r2,[r1]
	
	ldr		r1, =0x1000b07c
	ldr		r2, =0x0
	str		r2,[r1]
	
;***************************************************************
;	Import some important variables for later use

    IMPORT |Image$$RO$$Base|    
	IMPORT |Image$$RO$$Limit|   
	IMPORT |Image$$RW$$Base|   
	IMPORT |Image$$RW$$Limit| 	
	IMPORT |Image$$ZI$$Base| 	
	IMPORT |Image$$ZI$$Limit|
;***************************************************************
;Self copy from FLASH to SDRAM

;	LDR		r0, =|Image$$RO$$Base|      
;	LDR		r1, =|Image$$RO$$Limit|      
;	LDR		r2, =|Image$$RW$$Base|      
;	LDR		r3, =|Image$$RW$$Limit|     

;	SUB 	r1, r1, r0
;	SUB		r3, r3, r2
;	ADD		r1, r1, r3
	
;	LDR		r2, =0x30000000   ;

	
;COPY
;	LDR		r3, [r0], #4
;	STR		r3, [r2], #4
;	SUBS	r1, r1,   #4
;	BNE		COPY



  	 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    ldr		r1, =0x1000b07c
	ldr		r2, =0xffffffff
	str		r2,[r1]
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	




REMAP
	ldr		r1, =0x11000010    				;REMAP 0 ADDRESS TO SDRAM
	ldr		r2, =0x0000000b    	
	str		r2, [r1]  
	
	
	; Copy RW & ZI to SDRAM
    IMPORT |Image$$RO$$Base|    
	IMPORT |Image$$RO$$Limit|   
	IMPORT |Image$$RW$$Base|   
	IMPORT |Image$$RW$$Limit| 	
	IMPORT |Image$$ZI$$Base| 	
	IMPORT |Image$$ZI$$Limit| 

	LDR r0, =|Image$$RO$$Limit| 	
	LDR r1, =|Image$$RW$$Base| 		
	LDR r3, =|Image$$ZI$$Base|
	 		   

	CMP r0, r1 
	BEQ %1
 
0 	CMP r1, r3 						; Copy init data
	LDRCC r2, [r0], #4
	STRCC r2, [r1], #4
	BCC %0

1 	LDR r1, =|Image$$ZI$$Limit| 	; Top of zero init segment
	MOV r2, #0

2 	CMP r3, r1 						; Zero init
	STRCC r2, [r3], #4
	BCC %2
	
	
	
	;	ldr		r1, =0x10000000
	;ldr		r2, =0xfffffffe
	;str		r2,[r1]
	;		ldr		r1, =0x10000008
	;ldr		r2, =0xEfffffff
	;str		r2,[r1]


	
;set up svc stack
 mov	r0, #0x13                ; make svc mode with all irqs disabled
; mov r0, #0xd3
	msr	cpsr_cxsf, r0		 
;	ldr sp, =0x1fff5000
	ldr sp, =0x1fff4e00
	; ldr sp, =0x30008000

	
; **********************************************************************
; * Get the address of the C entry point.
; **********************************************************************

	ldr lr, =c_entry
	
; **********************************************************************
; * Enable the interrupt while staying in the supervisor mode
; **********************************************************************
  mov r0, #0x12
;  mov r0, #0xd2
  msr cpsr_cxsf, r0
  ldr sp, =0x1fff5000
  ;ldr sp, =0x30008400


;	 mov r0, #0xd3

  MOV	r0, #Mode_Svc:OR:F_Bit
  MSR	cpsr_c, r0
;	LDR r0, =|Image$$RO$$Base| 	
;	LDR r1, =|Image$$ZI$$Limit| 	

	MOV 	pc, lr
	
	;/*************************************************/
	


undefined_instruction
	mov	r6, #3
	b	reset

software_interrupt
	mov	r6, #4
	b	reset

prefetch_abort
	mov	r6, #5
	b	reset

data_abort           
	mov	r6, #6
	b	reset

not_used
	;/* we *should* never reach this */
	mov	r6, #7
	b	reset

irq
  LDR lr, =c_entry
  MOV 	pc, lr

fiq
	mov	r6, #9
	b reset
	
	
		IMPORT  do_irq
	EXPORT  irq_handler
irq_handler
	SUB	lr, lr, #4            
	STMFD	sp!, {r0-r12, lr}        ; push r0-r12 register file and lr( pc return address )
 
	MRS 	r4, spsr        
	STMFD 	sp!, {r4}                ; push current spsr_cxsf_irq ( =cpsr_svc )

	BL	do_irq			 ; goto C handler
	
	LDMFD 	sp!, {r4}                ; get cpsr_svc from stack
	MSR     spsr_cxsf, r4		 ; prepare spsr_cxsf to return svc mode	

	LDMFD	sp!, {r0-r12, pc}^       ; recover r0-r12 and pc from stack, cpsr also
	
	END
	b	reset
	END