📄 hardware.h
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#ifndef _HARDWARE_H
#define _HARDWARE_H
#include "hardware_reg.h"
#define GFD_ASIXOS
//***************************************
//PMU module clk
//*************************************
#define CLK_INTC (1 << 14)
#define CLK_PMU (1 << 13)
#define CLK_RTC (1 << 12)
#define CLK_GPT (1 << 11)
#define CLK_SPI (1 << 10)
#define CLK_UART0 (1 << 9)
#define CLK_UART1 (1 << 8)
#define CLK_GPIO (1 << 7)
#define CLK_MMC (1 << 6)
#define CLK_AC97 (1 << 5)
#define CLK_DMA (1 << 4)
#define CLK_MMA (1 << 3)
#define CLK_LCDC (1 << 2)
#define CLK_ESRAM (1 << 1)
#define CLK_EMI (1)
/*************************************
macros for INTC
*************************************/
/*interrupt resources */
#define INT_RTC 31
#define INT_DMA 30
#define INT_EMI 29
#define INT_GPT 28
#define INT_USB 27
#define INT_SPI 26
#define INT_MMC 25
#define INT_UART0 24
#define INT_UART1 23
#define INT_I2C 22
#define INT_AC97 21
#define INT_MMA 20
#define INT_EXT17 19
#define INT_EXT16 18
#define INT_EXT15 17
//#define INT_NONE 16
#define INT_EXT0 15
#define INT_EXT1 1
#define INT_EXT2 13
#define INT_EXT3 12
#define INT_EXT4 11
#define INT_EXT5 10
#define INT_TP 9
#define INT_EXT7 8
#define INT_EXT8 7
#define INT_EXT9 6
#define INT_EXT10 5
#define INT_EXT11 4
#define INT_EXT12 3
#define INT_EXT13 2
#define INT_EXT14 14
/*************************************
macros for RTC
*************************************/
#define RTC_CTRL_RTCEN 0XFFFFFFFE //bit0 to be 0 is effective
#define RTC_CTRL_WDOGEN 0X02 //bit1 to be 1 is effective
#define RTC_IEN_SAMON 0X01 //Sample int enable on
#define RTC_IEN_SECON 0X02 //Second roll int enable on
#define RTC_IEN_MINON 0x04 //Minute roll int enable on
#define RTC_IEN_ALMON 0X08 //Alarm int enable on
#define RTC_IEN_WDOGON ~(1 << 4) //Watchdog int enable on
#define RTC_IEN_RESET 0X20 //When watchdog timeout,reset request to reset module enable bit
#define RTC_ISTAS_SAM 0X01
#define RTC_ISTAS_SEC 0X02
#define RTC_ISTAS_MIN 0X04
#define RTC_ISTAS_ALM 0X08
#define RTC_ISTAS_WDOG 0X10
#define RTC_WSVCE_VAL 0xAAAA
/****************************************
macros for GPT
****************************************/
#define GPT1_CNTL_GPTEN 0X01
#define GPT1_CNTL_NOCLK 0X00
#define GPT1_CNTL_SYSCLK (0X01 << 1)
#define GPT1_CNTL_SYSCLK8 (0X02 << 1)
#define GPT1_CNTL_SYSCLK16 (0X03 << 1)
#define GPT1_CNTL_COMIEN 0X10
#define GPT1_CNTL_NOCAP 0X00
#define GPT1_CNTL_CAPUP (0X01 << 6)
#define GPT1_CNTL_CAPDOWN (0X02 << 6)
#define GPT1_CNTL_CAPALL (0X03 << 6)
#define GPT1_CNTL_FREERUN (1 << 8)
#define GPT1_CNTL_PWM (1 << 18)
#define GPT1_CNTL_SWR (1 << 15)
#define GPT1_STAS_CMP 0X01
#define GPT1_STAS_CAP 0X02
/*****************************************
macros for UART
*****************************************/
#define UART1_IER_MODEM 0X01
#define UART1_IER_RLS 0X02
#define UART1_IER_THR 0X04
#define UART1_IER_RDA 0X08
#define UART1_IIR_MODEM 0X00
#define UART1_IIR_THR 0X01
#define UART1_IIR_RDA 0X02
#define UART1_IIR_RLS 0X03
#define UART1_IIR_TMO 0X06
#define UART1_LCR_DIV 0X80
/*****************************************
macros for PWM
*****************************************/
#define PWM1_CNTL_PWM (1 << 18)
#define PWM1_CNTL_DMA (1 << 17)
#define PWM1_CNTL_RST (1 << 16)
#define PWM1_CNTL_CLK32 (1 << 15)
#define PWM1_CNTL_IEN (1 << 13)
#define PWM1_CNTL_WOK (1 << 12)
#define PWM1_CNTL_PWMEN (1 << 11)
#define PWM1_CNTL_NOREP 0X00
#define PWM1_CNTL_REP2 (0X01 << 9)
#define PWM1_CNTL_REP3 (0X10 << 9)
#define PWM1_CNTL_REP7 (0X11 << 9)
#define PWM1_CNTL_32K 0X00
#define PWM1_CNTL_16K 0X01
#define PWM1_CNTL_8K 0X10
#define PWM1_CNTL_4K 0X11
////////////////////////////////////////////////////////////////
#define EMI_SRAM_REGBASE 0x11000000 //Sdram sram register base;
#define EMI_NAND_REGBASE 0x11000100 //NAND FLASH register base;
#define EMIADDR_SMCONF ( EMI_SRAM_REGBASE+0x00 ) //adress of sram time_sequence register
#define EMIADDR_CSGBAB ( EMI_SRAM_REGBASE+0x04 ) //adress of CSA and CSB chip select register
#define EMIADDR_CSGBCD ( EMI_SRAM_REGBASE+0X08 ) //adress of CSC and CSD chip select register
#define EMIADDR_CSGBEF ( EMI_SRAM_REGBASE+0Xc ) //adress of CSE and CSF chip select register
#define EMIADDR_REMAP ( EMI_SRAM_REGBASE+0X10 ) //Remap register select boot memory
#define EMIADDR_SDCONF1 ( EMI_SRAM_REGBASE+0X14 ) //sram and adram time_sequence register I
#define EMIADDR_SDCONF2 ( EMI_SRAM_REGBASE+0X18 ) //sram and adram time_sequence register II
#define EMIADDR_NANDADDR ( EMI_NAND_REGBASE+0X00 ) //adress of Nand Flash adress register
#define EMIADDR_NANDCOM ( EMI_NAND_REGBASE+0X04 ) //adress of Nand Flash control register
#define EMIADDR_NANDSTATUS ( EMI_NAND_REGBASE+0X0c ) //adress of Nand Flash status register
#define EMIADDR_NANDERRORADDR1 ( EMI_NAND_REGBASE+0X10 ) //adress of Nand Flash error register I
#define EMIADDR_NANDERRORADDR2 ( EMI_NAND_REGBASE+0X14 ) //adress of Nand Flash error register II
#define EMIADDR_NANDCONF ( EMI_NAND_REGBASE+0X18 ) //adress of Nand Flash config register
#define EMIADDR_NANDINTR ( EMI_NAND_REGBASE+0X1c ) //Int clear
#define EMIADDR_NANDFINECC ( EMI_NAND_REGBASE+0X20 ) //ECC complish
#define EMIADDR_NANDIDLE ( EMI_NAND_REGBASE+0X24 ) //Compish register
#define EMI_NAND_DATA 0x11000200
#define HA_ERRORBASE_EMI 0X28050000
/*****************************************
macros for EMI
*****************************************/
#define EMIADDR_CSGBAB_val 0x24002000 //base adress of csa:0x20000000
//base adress of csb:0x24000000(none now)
#define EMIADDR_CSGBCD_val 0x2c002800 //base adress of csc:0x28000000
//base adress of csc:0x2C000000(none now)
#define EMIADDR_CSGBEF_val 0x34003000 //base adress of csc:0x30000000
//base adress of csc:0x34000000
#define EMIADDR_SMCONF_val 0x9b010333 //write cycle: 3 read cycle:3
//csa:32_bit sram
//csb:none
//csc:32_bit sram
//csd:none
//cde:16_bit sdram
//cdf:32 bit sdram
#define EMIADDR_SDCONF1_val 0x0110a077 //12 row * 9 column
//non_Interleaved Address Mode
//2 row every flesh clock edge
//hang_up after 64 clocks after last access
//CAS = 2 clock
//3 clock between precharge and active command
//4 clock between active and write/read command toward the same bank
//7 clock between refresh command and later commands
#define EMIADDR_SDCONF2_val 0x80001860 //Initialize sdam;
//refresh cyccle:64*0x186 clocks
//refresh all rows once a time
#define EMIADDR_NANDCONF_VAL 0x02200aaa //4 address 0x1aa3aa
//Trr 10 cycles
//Tclh 2 cycles
//Talh 2 cycles
//Twh 3 cycles
//Read_width 10 cycles
//Writ_width 10 cycles
/****************************************
macros for write and read registers
****************************************/
#define write_reg(reg, data) \
*(RP)reg = data
#define read_reg(reg) \
*(RP)reg
/****************************************
macros for interrupt operation
****************************************/
#define set_plevel(plevel) \
*(RP)INTC_PLV = plevel
#define set_int_force(intnum) \
*(RP)INTC_IFCE = (1 << intnum)
#define irq_enable(intnum) \
*(RP)INTC_IEN |= (1 << intnum)
#define irq_disable( intnum) \
*(RP)INTC_IEN &= ~(1<< intnum)
#define mask_irq(intnum) \
*(RP)INTC_IMSK |= (1 << intnum)
#define unmask_irq(intnum) \
*(RP)INTC_IMSK &= ~(1 << intnum)
#define mask_all_irq() \
*(RP)INTC_IMSK = 0xFFFFFFFF
#define unmask_all_irq() \
*(RP)INTC_IMSK = 0x00000000
#define enable_all_irq() \
*(RP)INTC_IEN = 0XFFFFFFFF
#define disable_all_irq() \
*(RP)INTC_IEN = 0X00000000
/****************************************
functions for all modules
****************************************/
#if 0
/*RTC*/
extern void init_rtc(void);
extern ER set_ymd(U32 year, U32 month, U32 day);
extern ER set_hms(U32 hour, U32 minute, U32 second);
extern ER get_ymd(U32* year, U32 * month, U32* day);
extern ER get_hms(U32* hour, U32* minute, U32* second);
extern ER set_alarmtime(U32 hour, U32 minute);
extern ER rtc_int_en(BOOL alarm, BOOL wdog, BOOL samp, BOOL minroll, BOOL secroll);
extern ER set_samp(U32 frequency);
extern ER set_wdog_cont(U32 count);
extern ER int_serv_rtc(void);
/*UART*/
extern ER init_uart1(U32 sysclk, U32 baudrate, U32 databit, U32 trigerlevel );
extern ER uart_int_en(U32 recie, U32 thrie);
extern ER int_serv_uart1(void);
extern ER HA_WR_UART1( U32 DATA );
/*GPT*/
extern ER init_gpt1(void);
extern ER gpt_int_en(U32 comp);
extern ER int_serv_gpt1(void);
/*PWM*/
extern ER init_pwm1(void);
extern ER int_serv_pwm(void);
/*LCDC*/
extern void init_LCD(void);
extern ER lcd_draw(U8 x1, U8 y1, U8 x2, U8 y2, U8 color);
/*INTC*/
extern ER init_intc( void );
/*GPIO*/
void port_test(void);
/*SPI*/
extern ER HA_INITSPI(void);
extern ER HA_SPI_HANDLE(void);
extern ER usbinit(void);
/*EMI*/
U32 HA_INIT_EMI(U32 gloabalvar_add);
ER clear(U32 tempadd, U32 num);
ER HA_EMI_WRIT(U32 add, U32 data);
ER HA_DMA_DATADEFINE(U32 beginadd, U32 num, U32 size);
U32 HA_DMA_DATADCHECK(U32 beginadd, U32 num, U32 size, U32 gloabalvar_add) ;
U32 HA_INIT_NANDFLASH(U32 gloabalvar_add);
ER HA_NAND_READ(void);
ER HA_NAND_WRIT(void);
/*EMI*/
int nand_rd_page(U32 nand_addr, U32*buffer, U32 do_read);
int nand_read_page_com (U32 page, U32 *buf);
int nand_write_page_com (U32 page, U32 *buf);
int nand_rd_block (U32 nand_addr, U32*buffer, U32 do_read);
int nand_erase_block(U32 blockhead);
ER HA_NandFlash(void);
ER HA_NandFlash_IdRead(U32 gloabalvar_add);
ER HA_NandFlash_BadBlcokHandler(void);
ER NorFlash_write( U32 Pageadd, U32 data );
ER NorFlash_read( U32 address);
ER NorFlash_unlock( U32 address);
ER NorFlash_idlejud(U32 address);
ER NorFlash_clearSR(void);
ER NorFlash_bolckerase(U32 blockadd);
ER NorFlash_Normal(U32 address);
/*pai calculate*/
void pai_print(void);
/*DMA*/
ER HA_InitDMAC(void);
ER HA_DMA_INITIAL_ONECHANNEL(U32 channelnum);
ER HA_DMA_TRANS(U32 srcadd, U32 destadd, U32 srcwidth, U32 destwidth, U32 srcsize, U32 channelnum, U32 transnum);
ER HA_DMA_TRANS_RX(U32 srcadd, U32 destadd, U32 srcwidth, U32 destwidth, U32 srcsize, U32 channelnum, U32 transnum);
ER HA_DMA_TRANS_TX(U32 srcadd, U32 destadd, U32 srcwidth, U32 destwidth, U32 srcsize, U32 channelnum, U32 transnum);
/*MMC*/
extern ER init_mmc(void );
extern ER Send_Cmd_Wait_Resp(U32 cmd,U32 arg,U32 com_dat_cont,U32 blk_len,U32 nob,U32 int_mask);
extern ER Mmc_Software_Reset( void);
extern ER Card_Registry(void);
extern ER Mmc_Block_Write_Dma(U32 nob,U32 address);
extern ER Mmc_Block_Read_Dma(U32 nob,U32 address);
extern ER Check_Card_Status(void);
extern ER Block_Write_polling(U32 rca,U32 nob,U32 address);
extern ER Block_Read_Polling(U32 rca,U32 nob,U32 address);
extern ER Stream_Read(U32 nob,U32 address);
extern ER Stream_Write(U32 nob,U32 address);
extern ER Write_Reg( U32 reg,U32 data);
extern ER Read_Reg(U32 reg);
extern ER MmcCard_Chect(void);
extern ER Check_Ocr_Reg(void);
//extern ER Mmc_reset_value_test(void);
extern HA_DMA_TRANS_RX(U32 srcadd, U32 destadd, U32 srcwidth, U32 destwidth, U32 srcsize, U32 channelnum, U32 transnum);
extern HA_DMA_TRANS_TX(U32 srcadd, U32 destadd, U32 srcwidth, U32 destwidth, U32 srcsize, U32 channelnum, U32 transnum);
/****************************************
for print function
****************************************/
extern ER print( U32 addr, U32 errsymb );
extern ER print_num( U32 addr, U32 num );
extern ER prints(char *s);
#endif //temp del...
#endif
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