m68328.h

国家ASIC工程中心使用的嵌入式操作系统

#define IWR_IRQ6	(1 << IRQ6_IRQ_NUM)	/* IRQ6 */
#define IWR_PEN		(1 << PEN_IRQ_NUM)	/* Pen Interrupt */
#define IWR_SPIS	(1 << SPIS_IRQ_NUM)	/* SPI Slave Interrupt */
#define IWR_TMR1	(1 << TMR1_IRQ_NUM)	/* Timer 1 interrupt */
#define IWR_IRQ7	(1 << IRQ7_IRQ_NUM)	/* IRQ7 */

/* 
 * Interrupt Status Register 
 */
#define ISR_ADDR	0xfffff30c
#define ISR		LONG_REF(ISR_ADDR)

#define ISR_SPIM 	(1 << SPIM _IRQ_NUM)	/* SPI Master interrupt */
#define	ISR_TMR2	(1 << TMR2_IRQ_NUM)	/* Timer 2 interrupt */
#define ISR_UART	(1 << UART_IRQ_NUM)	/* UART interrupt */	
#define	ISR_WDT		(1 << WDT_IRQ_NUM)	/* Watchdog Timer interrupt */
#define ISR_RTC		(1 << RTC_IRQ_NUM)	/* RTC interrupt */
#define	ISR_KB		(1 << KB_IRQ_NUM)	/* Keyboard Interrupt */
#define ISR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator int. */
#define	ISR_INT0	(1 << INT0_IRQ_NUM)	/* External INT0 */
#define	ISR_INT1	(1 << INT1_IRQ_NUM)	/* External INT1 */
#define	ISR_INT2	(1 << INT2_IRQ_NUM)	/* External INT2 */
#define	ISR_INT3	(1 << INT3_IRQ_NUM)	/* External INT3 */
#define	ISR_INT4	(1 << INT4_IRQ_NUM)	/* External INT4 */
#define	ISR_INT5	(1 << INT5_IRQ_NUM)	/* External INT5 */
#define	ISR_INT6	(1 << INT6_IRQ_NUM)	/* External INT6 */
#define	ISR_INT7	(1 << INT7_IRQ_NUM)	/* External INT7 */
#define ISR_IRQ1	(1 << IRQ1_IRQ_NUM)	/* IRQ1 */
#define ISR_IRQ2	(1 << IRQ2_IRQ_NUM)	/* IRQ2 */
#define ISR_IRQ3	(1 << IRQ3_IRQ_NUM)	/* IRQ3 */
#define ISR_IRQ6	(1 << IRQ6_IRQ_NUM)	/* IRQ6 */
#define ISR_PEN		(1 << PEN_IRQ_NUM)	/* Pen Interrupt */
#define ISR_SPIS	(1 << SPIS_IRQ_NUM)	/* SPI Slave Interrupt */
#define ISR_TMR1	(1 << TMR1_IRQ_NUM)	/* Timer 1 interrupt */
#define ISR_IRQ7	(1 << IRQ7_IRQ_NUM)	/* IRQ7 */

/* 'EZ328-compatible definitions */
#define ISR_SPI	ISR_SPIM
#define ISR_TMR	ISR_TMR1

/* 
 * Interrupt Pending Register 
 */
#define IPR_ADDR	0xfffff310
#define IPR		LONG_REF(IPR_ADDR)

#define IPR_SPIM 	(1 << SPIM _IRQ_NUM)	/* SPI Master interrupt */
#define	IPR_TMR2	(1 << TMR2_IRQ_NUM)	/* Timer 2 interrupt */
#define IPR_UART	(1 << UART_IRQ_NUM)	/* UART interrupt */	
#define	IPR_WDT		(1 << WDT_IRQ_NUM)	/* Watchdog Timer interrupt */
#define IPR_RTC		(1 << RTC_IRQ_NUM)	/* RTC interrupt */
#define	IPR_KB		(1 << KB_IRQ_NUM)	/* Keyboard Interrupt */
#define IPR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator int. */
#define	IPR_INT0	(1 << INT0_IRQ_NUM)	/* External INT0 */
#define	IPR_INT1	(1 << INT1_IRQ_NUM)	/* External INT1 */
#define	IPR_INT2	(1 << INT2_IRQ_NUM)	/* External INT2 */
#define	IPR_INT3	(1 << INT3_IRQ_NUM)	/* External INT3 */
#define	IPR_INT4	(1 << INT4_IRQ_NUM)	/* External INT4 */
#define	IPR_INT5	(1 << INT5_IRQ_NUM)	/* External INT5 */
#define	IPR_INT6	(1 << INT6_IRQ_NUM)	/* External INT6 */
#define	IPR_INT7	(1 << INT7_IRQ_NUM)	/* External INT7 */
#define IPR_IRQ1	(1 << IRQ1_IRQ_NUM)	/* IRQ1 */
#define IPR_IRQ2	(1 << IRQ2_IRQ_NUM)	/* IRQ2 */
#define IPR_IRQ3	(1 << IRQ3_IRQ_NUM)	/* IRQ3 */
#define IPR_IRQ6	(1 << IRQ6_IRQ_NUM)	/* IRQ6 */
#define IPR_PEN		(1 << PEN_IRQ_NUM)	/* Pen Interrupt */
#define IPR_SPIS	(1 << SPIS_IRQ_NUM)	/* SPI Slave Interrupt */
#define IPR_TMR1	(1 << TMR1_IRQ_NUM)	/* Timer 1 interrupt */
#define IPR_IRQ7	(1 << IRQ7_IRQ_NUM)	/* IRQ7 */

/* 'EZ328-compatible definitions */
#define IPR_SPI	IPR_SPIM
#define IPR_TMR	IPR_TMR1


/**********
 *
 * 0xFFFFF6xx -- General-Purpose Timer
 *
 **********/

/* 
 * Timer Control register
 */
#define TCTL_ADDR	0xfffff600
#define TCTL		WORD_REF(TCTL_ADDR)

#define	TCTL_TEN		0x0001	/* Timer Enable  */
#define TCTL_CLKSOURCE_MASK 	0x000e	/* Clock Source: */
#define   TCTL_CLKSOURCE_STOP	   0x0000	/* Stop count (disabled)    */
#define   TCTL_CLKSOURCE_SYSCLK	   0x0002	/* SYSCLK to prescaler      */
#define   TCTL_CLKSOURCE_SYSCLK_16 0x0004	/* SYSCLK/16 to prescaler   */
#define   TCTL_CLKSOURCE_TIN	   0x0006	/* TIN to prescaler         */
#define   TCTL_CLKSOURCE_32KHZ	   0x0008	/* 32kHz clock to prescaler */
#define TCTL_IRQEN		0x0010	/* IRQ Enable    */
#define TCTL_OM			0x0020	/* Output Mode   */
#define TCTL_CAP_MASK		0x00c0	/* Capture Edge: */
#define	  TCTL_CAP_RE		0x0040		/* Capture on rizing edge   */
#define   TCTL_CAP_FE		0x0080		/* Capture on falling edge  */
#define TCTL_FRR		0x0010	/* Free-Run Mode */

/* '328-compatible definitions */
#define TCTL1_ADDR	TCTL_ADDR
#define TCTL1		TCTL

/*
 * Timer Prescaler Register
 */
#define TPRER_ADDR	0xfffff602
#define TPRER		WORD_REF(TPRER_ADDR)

/* '328-compatible definitions */
#define TPRER1_ADDR	TPRER_ADDR
#define TPRER1		TPRER

/*
 * Timer Compare Register
 */
#define TCMP_ADDR	0xfffff604
#define TCMP		WORD_REF(TCMP_ADDR)

/* '328-compatible definitions */
#define TCMP1_ADDR	TCMP_ADDR
#define TCMP1		TCMP

/*
 * Timer Capture register
 */
#define TCR_ADDR	0xfffff606
#define TCR		WORD_REF(TCR_ADDR)

/* '328-compatible definitions */
#define TCR1_ADDR	TCR_ADDR
#define TCR1		TCR

/*
 * Timer Counter Register
 */
#define TCN_ADDR	0xfffff608
#define TCN		WORD_REF(TCN_ADDR)

/* '328-compatible definitions */
#define TCN1_ADDR	TCN_ADDR
#define TCN1		TCN

/*
 * Timer Status Register
 */
#define TSTAT_ADDR	0xfffff60a
#define TSTAT		WORD_REF(TSTAT_ADDR)

#define TSTAT_COMP	0x0001		/* Compare Event occurred */
#define TSTAT_CAPT	0x0001		/* Capture Event occurred */

/* '328-compatible definitions */
#define TSTAT1_ADDR	TSTAT_ADDR
#define TSTAT1		TSTAT


/**********
 *
 * 0xFFFFFBxx -- Real-Time Clock (RTC)
 *
 **********/

/*
 * RTC Hours Minutes and Seconds Register
 */
#define RTCTIME_ADDR	0xfffffb00
#define RTCTIME		LONG_REF(RTCTIME_ADDR)

#define RTCTIME_SECONDS_MASK	0x0000003f	/* Seconds */
#define RTCTIME_SECONDS_SHIFT	0
#define RTCTIME_MINUTES_MASK	0x003f0000	/* Minutes */
#define RTCTIME_MINUTES_SHIFT	16
#define RTCTIME_HOURS_MASK	0x1f000000	/* Hours */
#define RTCTIME_HOURS_SHIFT	24

/*
 *  RTC Alarm Register 
 */
#define RTCALRM_ADDR    0xfffffb04
#define RTCALRM         LONG_REF(RTCALRM_ADDR)

#define RTCALRM_SECONDS_MASK    0x0000003f      /* Seconds */
#define RTCALRM_SECONDS_SHIFT   0
#define RTCALRM_MINUTES_MASK    0x003f0000      /* Minutes */
#define RTCALRM_MINUTES_SHIFT   16
#define RTCALRM_HOURS_MASK      0x1f000000      /* Hours */
#define RTCALRM_HOURS_SHIFT     24

/*
 * RTC Control Register
 */
#define RTCCTL_ADDR	0xfffffb0c
#define RTCCTL		WORD_REF(RTCCTL_ADDR)

#define RTCCTL_384	0x0020	/* Crystal Selection */
#define RTCCTL_ENABLE	0x0080	/* RTC Enable */

/* 'EZ328-compatible definitions */
#define RTCCTL_XTL	RTCCTL_384
#define RTCCTL_EN	RTCCTL_ENABLE

/*
 * RTC Interrupt Status Register 
 */
#define RTCISR_ADDR	0xfffffb0e
#define RTCISR		WORD_REF(RTCISR_ADDR)

#define RTCISR_SW	0x0001	/* Stopwatch timed out */
#define RTCISR_MIN	0x0002	/* 1-minute interrupt has occured */
#define RTCISR_ALM	0x0004	/* Alarm interrupt has occured */
#define RTCISR_DAY	0x0008	/* 24-hour rollover interrupt has occured */
#define RTCISR_1HZ	0x0010	/* 1Hz interrupt has occured */
#define RTCISR_SAM3	0x0800	/* 32Hz interrupt has occured */

/*
 * RTC Interrupt Enable Register
 */
#define RTCIENR_ADDR	0xfffffb10
#define RTCIENR		WORD_REF(RTCIENR_ADDR)

#define RTCIENR_SW	0x0001	/* Stopwatch interrupt enable */
#define RTCIENR_MIN	0x0002	/* 1-minute interrupt enable */
#define RTCIENR_ALM	0x0004	/* Alarm interrupt enable */
#define RTCIENR_DAY	0x0008	/* 24-hour rollover interrupt enable */
#define RTCIENR_1HZ	0x0010	/* 1Hz interrupt enable */
#define RTCIENR_SAM3 0x0800	/* 32Hz interrupt enable */
#define RTCIENR_256HZ	0x8000	/* 256hz interrupt enable */

/* 
 * Stopwatch Minutes Register
 */
#define STPWCH_ADDR	0xfffffb12
#define STPWCH		WORD_REF(STPWCH)

#define STPWCH_CNT_MASK	 0x00ff	/* Stopwatch countdown value */
#define SPTWCH_CNT_SHIFT 0

/////////////////////////////////////////////////////////////////////////////
#define M328BASE        0xFFF000

/* SIM28 System Configuration Registers */
#define M328_SCR        (M328BASE+0x000)

/* CS Group Mask Registers have been deleted for EZ */
					
#define M328_CSA0       (M328BASE+0x110)    /* Group A CS Registers */
#define M328_CSB0       (M328BASE+0x112)    /* Group B CS Registers */
#define M328_CSC0       (M328BASE+0x114)    /* Group C CS Registers */
#define M328_CSD0       (M328BASE+0x116)    /* Group D CS Registers */

/* New support on Emulation Chip Select Register for EZ */
#define M328_EMUCS      (M328BASE+0x118)

/* PLL Registers */
#define M328_PLLCR      (M328BASE+0x200)        /* Control Reg */
#define M328_PLLFSR     (M328BASE+0x202)        /* Freq Select Reg */
#define M328_PLLTSR     (M328BASE+0x204)        /* Test Reg */

/* Power Control Registers */
#define M328_PCTLR      (M328BASE+0x206)        /* Control Reg */

/* Interrupt Registers */
#define M328_IVR        (M328BASE+0x300)        /* Interrupt Vector Reg */
#define M328_ICR        (M328BASE+0x302)        /* Interrupt Control Reg */
#define M328_IMR        (M328BASE+0x304)        /* Interrupt Mask Reg */
#define M328_ISR        (M328BASE+0x30C)        /* Interrupt Status Reg */
#define M328_IPR        (M328BASE+0x310)        /* Interrupt Pending Reg */

/* PIO Registers */
					/* Port A Registers */
#define M328_PADIR      (M328BASE+0x400)        /* Direction Reg */
#define M328_PADATA     (M328BASE+0x401)        /* Data Reg */
#define M328_PAPUEN     (M328BASE+0x402)        /* New Pullup Enable Reg */
					/* Port B Registers */
#define M328_PBDIR      (M328BASE+0x408)        /* Direction Reg */
#define M328_PBDATA     (M328BASE+0x409)        /* Data Reg */
#define M328_PBPUEN     (M328BASE+0x40A)        /* New Pullup Enable Reg */
#define M328_PBSEL      (M328BASE+0x40b)        /* Select Reg */
					/* Port C Registers */
#define M328_PCDIR      (M328BASE+0x410)        /* Direction Reg */
#define M328_PCDATA     (M328BASE+0x411)        /* Data Reg */
#define M328_PCPDEN     (M328BASE+0x412)        /* New Pulldown Enable Reg */
#define M328_PCSEL      (M328BASE+0x413)        /* Select Reg */