m68328.h

国家ASIC工程中心使用的嵌入式操作系统

/****************************************************************
 *  Copyright (C) Asic Center. 2001
 *  All Rights Reserved
 *
 *  Filename : EPSONC33.h
 *  Function : hardware abstract layer(HAL)
 *  Revision :
 *		2002/4/17	PESSIA	Create this file
 *****************************************************************/
#ifndef _M68328_H
#define _M68328_H

#include "DBCFG.H"
//#include "hardware\dbcfg.h"  //GFD
#include "itron.h"

extern	UW g_cpsr2r0;
extern	void enable_irq(void);
extern	void disable_irq(void);
extern	void erter_crtical_section(void);
extern	void exit_crtical_section(void);
extern	void reti(void);



#if ( CHIP == GARFIELD )  
/*
  * ENABLE_IRQ  --- set int level in SR to 0.
  */
#define ENABLE_INT	enable_irq()			
	
/*
  * DISABLE_IRQ  --- set int level in SR to 6.
  */
#define DISABLE_INT	 disable_irq()

/*
  * ENTER_CRITICAL_SECTION --- push sr and IL = 7
  */
#define ENTER_CRITICAL_SECTION erter_crtical_section()

/*
  * EXIT_CRITICAL_SECTION --- IL = 0 and pop sr
  */
#define EXIT_CRITICAL_SECTION exit_crtical_section()
/*
  * SAVE_CURTSK_SP ------ g_pCurTsk->uwSP = sp
  * RESTORE_CURTSK_SP ---sp = g_pCurTsk->uwSP
  */
#define CURTSK_SP	16
#define SAVE_CURTSK_SP  save_current_sp()
#define RESTORE_CURTSK_SP restore_current_sp()
/*
  * GET_RETURN_VALUE_FROM_STACK:
  *     r10 is used to save return value, 
  *     and change stack point ( sp )
  */

#define GET_RETURN_VALUE_FROM_STACK get_current_value_from_stack()
 /* PUSH_NULL --- push null into stack
  * POP_NULL	 --- pop null from stack
  */
#define PUSH_NULL  push_null()	
#define POP_NULL   pop_null()	
/*
  * PUSH_ALL_COMM_REG ---to save all common registers ( which include 
  *     all information about current task ) into stack when interrupt occurs.
  * POP_ALL_COMM_REG   ---to restore all common registers.
  */
#define PUSH_ALL_COMM_REG push_all_comm_reg()
#define POP_ALL_COMM_REG  pop_all_comm_reg()
#define POP_ALL_COMM_REG_AND_INT_RETI pop_all_comm_reg_and_int_reti()
/*
  * PUSH_CALLEE_SAVED_REG --- to save special registers (which must 
  *     be saved by callee while not caller ) into stack while function-calling
  *     occurs.
  * POP_CALLEE_SAVED_REG --- to restore them.
  */
/*
#define PUSH_CALLEE_SAVED_REG \
	PUSH_ALL_COMM_REG
#define POP_CALLEE_SAVED_REG \
	POP_ALL_COMM_REG
*/
#define PUSH_CALLEE_SAVED_REG push_callee_saved_reg()
#define POP_CALLEE_SAVED_REG pop_callee_saved_reg()

/*
  * MOV_R1TOR0 --- mov r1 to r0 in order to return the value back to function correctly 
  */
#define MOV_R1TOR0	move_r1tor0()

/*
  * PUSH_PSR --- save PSR into stack
  * POP_PSR	--- restore PSR from stack
  */
	 
#define PUSH_PSR  (g_cpsr2r0=push_cpsr())
#define POP_PSR   pop_cpsr(g_cpsr2r0)

UW ent_cri(void);
void ret_cri(UW psr);

/* called at the first line of ISR */
#define EXTEND_PSR_TO_32  extend_psr_to_32()
/*
  * RETI --- return from interrupt( pop PC&PSR).
  */
#define RETI  reti()
#define INT_RETI int_reti()
/*
 * ent_cri --- return PSR back and level up interrupt level
 * ret_cri --- restore PSR
 *
 * note : they are used in system call, to avoid 
 *		  change stack which affects local variables.
 */
//extern unsigned short ent_cri( void );
//extern void ret_cri( unsigned short psr );

/* in c33209 , INT_RETI ==  RETI */


/*
  * Interrupt Context Information :
  *    it is built by PUSH_ALL_COMM_REG
  */
typedef struct _tag_T_SAVEDREG
{
    unsigned long   r[13];     		// General-purpose register 
    unsigned long   psr;       		// Processor status register
    unsigned long   r14;
    void (*pc)();   		// Program counter/
} T_SAVEDREG;

/*
  * Minimum Context Information :
  *    it is built by 
  *			PUSH_CALLEE_SAVED_REG;
  *			PUSH_NULL;
  */
typedef struct  _tag_T_SAVEDREG_MIN
{
    unsigned long   returnvalue;       // return value
    unsigned long   r[11];      	// General-purpose register
    unsigned long   psr;       		// Processor status register
    void (*pc)();   		// Program counter
} T_SAVEDREG_MIN;

/*
  * returnvalue --- to provide an accordant interrface of return-value
  *    from different cpus.
  */
//#define returnvalue	D0

//#define INI_PSR     0x2000      	// initial flag (%PSR value)
//gfd modified for svc mode
#define INI_PSR     0x53        	// default is interrupt enable
                                   		
#define WORD_REF(addr) (*((volatile unsigned short*)addr))
#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
#define LONG_REF(addr) (*((volatile unsigned long*)addr))


/**********
 *
 * 0xFFFFF3xx -- Interrupt Controller
 *
 **********/

/* 
 * Interrupt Vector Register
 */
#define IVR_ADDR	0xfffff300
#define IVR		BYTE_REF(IVR_ADDR)

#define IVR_VECTOR_MASK 0xF8

/*
 * Interrupt control Register
 */
#define ICR_ADDR	0xffff302
#define ICR		WORD_REF(ICR_ADDR)

#define ICR_ET6		0x0100	/* Edge Trigger Select for IRQ6 */
#define ICR_ET3		0x0200	/* Edge Trigger Select for IRQ3 */
#define ICR_ET2		0x0400	/* Edge Trigger Select for IRQ2 */
#define ICR_ET1		0x0800	/* Edge Trigger Select for IRQ1 */
#define ICR_POL6	0x1000	/* Polarity Control for IRQ6 */
#define ICR_POL3	0x2000	/* Polarity Control for IRQ3 */
#define ICR_POL2	0x4000	/* Polarity Control for IRQ2 */
#define ICR_POL1	0x8000	/* Polarity Control for IRQ1 */

/*
 * Interrupt Mask Register
 */
#define IMR_ADDR	 0xfffff304
#define IMR		LONG_REF(IMR_ADDR)
 
/*
 * Define the names for bit positions first. This is useful for
 * request_irq
 */
#define SPIM_IRQ_NUM	0	/* SPI Master interrupt */
#define	TMR2_IRQ_NUM	1	/* Timer 2 interrupt */
#define UART_IRQ_NUM	2	/* UART interrupt */	
#define	WDT_IRQ_NUM	3	/* Watchdog Timer interrupt */
#define RTC_IRQ_NUM	4	/* RTC interrupt */
#define	KB_IRQ_NUM	6	/* Keyboard Interrupt */
#define PWM_IRQ_NUM	7	/* Pulse-Width Modulator int. */
#define	INT0_IRQ_NUM	8	/* External INT0 */
#define	INT1_IRQ_NUM	9	/* External INT1 */
#define	INT2_IRQ_NUM	10	/* External INT2 */
#define	INT3_IRQ_NUM	11	/* External INT3 */
#define	INT4_IRQ_NUM	12	/* External INT4 */
#define	INT5_IRQ_NUM	13	/* External INT5 */
#define	INT6_IRQ_NUM	14	/* External INT6 */
#define	INT7_IRQ_NUM	15	/* External INT7 */
#define IRQ1_IRQ_NUM	16	/* IRQ1 */
#define IRQ2_IRQ_NUM	17	/* IRQ2 */
#define IRQ3_IRQ_NUM	18	/* IRQ3 */
#define IRQ6_IRQ_NUM	19	/* IRQ6 */
#define PEN_IRQ_NUM	20	/* Pen Interrupt */
#define SPIS_IRQ_NUM	21	/* SPI Slave Interrupt */
#define TMR1_IRQ_NUM	22	/* Timer 1 interrupt */
#define IRQ7_IRQ_NUM	23	/* IRQ7 */

/* '328-compatible definitions */
#define SPI_IRQ_NUM	SPIM_IRQ_NUM
#define TMR_IRQ_NUM	TMR1_IRQ_NUM
 
/*
 * Here go the bitmasks themselves
 */
#define IMR_MSPIM 	(1 << SPIM _IRQ_NUM)	/* Mask SPI Master interrupt */
#define	IMR_MTMR2	(1 << TMR2_IRQ_NUM)	/* Mask Timer 2 interrupt */
#define IMR_MUART	(1 << UART_IRQ_NUM)	/* Mask UART interrupt */	
#define	IMR_MWDT	(1 << WDT_IRQ_NUM)	/* Mask Watchdog Timer interrupt */
#define IMR_MRTC	(1 << RTC_IRQ_NUM)	/* Mask RTC interrupt */
#define	IMR_MKB		(1 << KB_IRQ_NUM)	/* Mask Keyboard Interrupt */
#define IMR_MPWM	(1 << PWM_IRQ_NUM)	/* Mask Pulse-Width Modulator int. */
#define	IMR_MINT0	(1 << INT0_IRQ_NUM)	/* Mask External INT0 */
#define	IMR_MINT1	(1 << INT1_IRQ_NUM)	/* Mask External INT1 */
#define	IMR_MINT2	(1 << INT2_IRQ_NUM)	/* Mask External INT2 */
#define	IMR_MINT3	(1 << INT3_IRQ_NUM)	/* Mask External INT3 */
#define	IMR_MINT4	(1 << INT4_IRQ_NUM)	/* Mask External INT4 */
#define	IMR_MINT5	(1 << INT5_IRQ_NUM)	/* Mask External INT5 */
#define	IMR_MINT6	(1 << INT6_IRQ_NUM)	/* Mask External INT6 */
#define	IMR_MINT7	(1 << INT7_IRQ_NUM)	/* Mask External INT7 */
#define IMR_MIRQ1	(1 << IRQ1_IRQ_NUM)	/* Mask IRQ1 */
#define IMR_MIRQ2	(1 << IRQ2_IRQ_NUM)	/* Mask IRQ2 */
#define IMR_MIRQ3	(1 << IRQ3_IRQ_NUM)	/* Mask IRQ3 */
#define IMR_MIRQ6	(1 << IRQ6_IRQ_NUM)	/* Mask IRQ6 */
#define IMR_MPEN	(1 << PEN_IRQ_NUM)	/* Mask Pen Interrupt */
#define IMR_MSPIS	(1 << SPIS_IRQ_NUM)	/* Mask SPI Slave Interrupt */
#define IMR_MTMR1	(1 << TMR1_IRQ_NUM)	/* Mask Timer 1 interrupt */
#define IMR_MIRQ7	(1 << IRQ7_IRQ_NUM)	/* Mask IRQ7 */

/* 'EZ328-compatible definitions */
#define IMR_MSPI	IMR_MSPIM
#define IMR_MTMR	IMR_MTMR1

/* 
 * Interrupt Wake-Up Enable Register
 */
#define IWR_ADDR	0xfffff308
#define IWR		LONG_REF(IWR_ADDR)

#define IWR_SPIM 	(1 << SPIM _IRQ_NUM)	/* SPI Master interrupt */
#define	IWR_TMR2	(1 << TMR2_IRQ_NUM)	/* Timer 2 interrupt */
#define IWR_UART	(1 << UART_IRQ_NUM)	/* UART interrupt */	
#define	IWR_WDT		(1 << WDT_IRQ_NUM)	/* Watchdog Timer interrupt */
#define IWR_RTC		(1 << RTC_IRQ_NUM)	/* RTC interrupt */
#define	IWR_KB		(1 << KB_IRQ_NUM)	/* Keyboard Interrupt */
#define IWR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator int. */
#define	IWR_INT0	(1 << INT0_IRQ_NUM)	/* External INT0 */
#define	IWR_INT1	(1 << INT1_IRQ_NUM)	/* External INT1 */
#define	IWR_INT2	(1 << INT2_IRQ_NUM)	/* External INT2 */
#define	IWR_INT3	(1 << INT3_IRQ_NUM)	/* External INT3 */
#define	IWR_INT4	(1 << INT4_IRQ_NUM)	/* External INT4 */
#define	IWR_INT5	(1 << INT5_IRQ_NUM)	/* External INT5 */
#define	IWR_INT6	(1 << INT6_IRQ_NUM)	/* External INT6 */
#define	IWR_INT7	(1 << INT7_IRQ_NUM)	/* External INT7 */
#define IWR_IRQ1	(1 << IRQ1_IRQ_NUM)	/* IRQ1 */
#define IWR_IRQ2	(1 << IRQ2_IRQ_NUM)	/* IRQ2 */
#define IWR_IRQ3	(1 << IRQ3_IRQ_NUM)	/* IRQ3 */